Merge branch 'features/lwip-SO_REUSEADDR' into 'master'
Enable SO_REUSEADDR in LWIP
Daniel initially asked me why this wasn't enabled, and I don't think I got any reasons against enabling this. If any, it makes porting existing software easier. Tuan needs it for UDP multicast as well.
Code changes are by Tuan: basically the enable for SO_REUSEADDR in LWIP as well as a bugfix in a bit of mbedTLS that gets enabled.
Adding -fstrict-volatile-bitfields to the CFLAGS/CXXFLAGS. Without this, gcc tries to access bitfields using the smallest possible methods (eg l8i to
grab an 8-bit field from a 32-bit). Our hardware does not like that. This flag tells gcc that if a bitfield is volatile, it should always use the type
the field is defined at (uint32_t in our case) to size its access to the field. This fixes accessing the hardware through the xxx_struct.h headers.
Ivan Grokhotkov [Thu, 15 Sep 2016 06:08:35 +0000 (14:08 +0800)]
Merge branch 'bugfix/github_deploy' into 'master'
fix deploy to GitHub
Previous change to gitlab-ci.yml moved setting of Gitlab ssh key to global before_script.
This together with the fact that we used `echo >>` instead of `echo >` to write to `id_rsa_base64` file caused wrong key to be used while pushing to GitHub.
Therefore:
- don't run default before_script before push_master_to_github job
- replace echo >> with echo > to avoid mistakes in the future
Only modify headers in soc/ .
Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
Merge branch 'bugfix/add_tx_flowcontrol' into 'master'
lwip: add socket tx flow control
This fix is used to solve wifi q full issue:
1. When wifi tx q is full, set tx_enable to false
2. When wifi tx q decrease 1/2 max length, set tx_enable to true again
3. esp_wifi_tx_enable return whether tx_enable is true
4. If esp_wifi_tx_enable return false, socket will be blocked
Ivan Grokhotkov [Tue, 13 Sep 2016 10:14:22 +0000 (18:14 +0800)]
Merge branch 'bugfix/spi_flash_unlock_once' into 'master'
components/spi_flash: call SPIUnlock once
This fixes the performance impact for spi_flash_write and spi_flash_erase.
With this change, NVS init in single core mode takes about 50ms (compared to >2seconds before that).
For dual core mode, we still spend on average 2ms for each spi_flash_ operation due to synchronization between CPUs, so NVS startup time is about 2 seconds in dual core mode.
Ivan Grokhotkov [Tue, 13 Sep 2016 07:16:36 +0000 (15:16 +0800)]
components/spi_flash: call SPIUnlock only once
This fixes the performance impact for spi_flash_write and spi_flash_erase.
With this change, NVS init in single core mode takes about 50ms (compared to >2seconds before that).
Ivan Grokhotkov [Tue, 13 Sep 2016 05:58:54 +0000 (13:58 +0800)]
Merge branch 'feature/dualcore_spi_flash_api' into 'master'
Dual core compatible spi flash APIs
Implementation of spi flash APIs which work in dual core mode.
This also includes other changes:
- fixes to FreeRTOS tasks.c made by Jeroen and me — these were originally made to fix issues with high priority tasks seen in WiFi stack, but were required to get stuff in ipc.c working as well
- initial base idea with two high-priority tasks was separated into a separate API — esp_ipc.h. That API allows one to run a function on the other CPU from a high-priority task. Because we don't have preemption across CPUs, this is currently not very fast: it requires on average half a tick until the second CPU switches to the high priority task. Currently that API can be either blocking, or non-blocking with queue length of 1. I haven't yet found a use case for arbitrary sized queue of IPC requests. Anyone who needs that can trivially add that later by replacing a binary semaphore with a generic queue.
With these changes i can run application with WiFi stack and NVS on both cores.
Merge branch 'feature/add_rom_comments' into 'master'
header files: modify rom code header files and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
jack [Wed, 31 Aug 2016 13:53:23 +0000 (21:53 +0800)]
header files: modify rom code and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions