[SystemZ] Use LLGT(R) instructions

This adds support for the 31-to-64-bit zero extension instructions
LLGT and LLGTR and uses them for code generation where appropriate.

Since this operation can also be performed via RISBG, we have to
update SystemZDAGToDAGISel::tryRISBGZero so that we prefer LLGT
over RISBG in case both are possible.  The patch includes some
simplification to the tryRISBGZero code; this is not intended
to cause any (further) functional change in codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286585 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in BSWAP opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286582 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector BSWAP test

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286579 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286578 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector UREM/SREM tests

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286577 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in UDIV opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286576 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector UDIV test

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286575 91177308-0d34-0410-b5e6-96231b3b80d8

[ARM] Add plumbing for GlobalISel

Add GlobalISel skeleton, up to the point where we can select a ret void.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286573 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] Make it work in the absence of hotness information

In this case the index page is sorted by the source location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286572 91177308-0d34-0410-b5e6-96231b3b80d8

Fix gold plugin after Error API changes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286571 91177308-0d34-0410-b5e6-96231b3b80d8

Fix examples files to reflect header split in r286566.

I missed these files in examples/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286570 91177308-0d34-0410-b5e6-96231b3b80d8

Add missing file from r286566

Add the new BitcodeWriter.h header, which was missed in my r286566
commit, and should fix all the bot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286569 91177308-0d34-0410-b5e6-96231b3b80d8

Split Bitcode/ReaderWriter.h into separate reader and writer headers

Summary:
Split ReaderWriter.h which contains the APIs into both the BitReader and
BitWriter libraries into BitcodeReader.h and BitcodeWriter.h.

This is to address Chandler's concern about sharing the same API header
between multiple libraries (BitReader and BitWriter). That concern is
why we create a single bitcode library in our downstream build of clang,
which led to r286297 being reverted as it added a dependency that
created a cycle only when there is a single bitcode library (not two as
in upstream).

Reviewers: mehdi_amini

Subscribers: dlj, mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D26502

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286566 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] PEPify opt-viewer.py

Reviewers: anemet

Subscribers: fhahn

Differential Revision: https://reviews.llvm.org/D26535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286564 91177308-0d34-0410-b5e6-96231b3b80d8

Fix build failure, update llvm-strings for the new Error API

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286563 91177308-0d34-0410-b5e6-96231b3b80d8

Prevent at compile time converting from Error::success() to Expected<T>

This would trigger an assertion at runtime otherwise.

Differential Revision: https://reviews.llvm.org/D26482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286562 91177308-0d34-0410-b5e6-96231b3b80d8

Make the Error class constructor protected

This is forcing to use Error::success(), which is in a wide majority
of cases a lot more readable.

Differential Revision: https://reviews.llvm.org/D26481

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286561 91177308-0d34-0410-b5e6-96231b3b80d8

CMake: make LLVM_OPTIMIZED_TABLEGEN friendly with LLVM_EXTERNAL_CLANG_SOURCE_DIR

This is need because of clang-tblgen

Differential Revision: https://reviews.llvm.org/D26483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286560 91177308-0d34-0410-b5e6-96231b3b80d8

[ADT/MathExtras] Make buildbot happy again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286559 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-strings: explicitly include cctype

Include the cctype header to try to fix windows bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286558 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-strings: introduce basic strings tool

This is a replacement to binutils' string tool.  It prints strings found in a
binary (object file, executable, or archive library).  It is rather bare and
not functionally equivalent, however, it lays the groundwork necessary for the
strings tool, enabling iterative development of features to reach feature
parity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286556 91177308-0d34-0410-b5e6-96231b3b80d8

[lli] Simplify the code a bit. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286555 91177308-0d34-0410-b5e6-96231b3b80d8

[IR/DataLayout] Simplify the code using PowerOf2Ceil. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286554 91177308-0d34-0410-b5e6-96231b3b80d8

AMDGPU: Attempt to fix build failure on x86-64 selfhost build

Remove redundant include file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286552 91177308-0d34-0410-b5e6-96231b3b80d8

[ADT/MathExtras] Add tests for PowerOf2Floor (previously untested).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286551 91177308-0d34-0410-b5e6-96231b3b80d8

Add a blank line for a test commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286550 91177308-0d34-0410-b5e6-96231b3b80d8

[ADT/MathExtras] Introduce PowerOf2Ceil.

To be used in lld (and probably somewhere else in llvm).

Differential Revision:  https://reviews.llvm.org/D26538

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286549 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm] Remove duplicate header from PassInfo.h

Reviewers: mehdi_amini

Differential Revision: https://reviews.llvm.org/D26533

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286546 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] Add column number support

With this the yellow (bubble) part of the remark shows up under the
corresponding expression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286545 91177308-0d34-0410-b5e6-96231b3b80d8

ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()

addSchedBarrierDeps() is supposed to add use operands to the ExitSU
node. The current implementation adds uses for calls/barrier instruction
and the MBB live-outs in all other cases. The use
operands of conditional jump instructions were missed.

Also added code to macrofusion to set the latencies between nodes to
zero to avoid problems with the fusing nodes lingering around in the
pending list now.

Differential Revision: https://reviews.llvm.org/D25140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286544 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] Display inlining context

When a function is inlined, each instance is optimized in their own
inlining context.  This can produce different remarks all pointing to
the same source line.

This adds a new column on the source view to display the inlining
context.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286537 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] Add option to set source directory

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286536 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] Mention Pygments in the description

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286535 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] Add syntax highlighting

Uses pygments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286532 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies"

This reverts commit r286171, it breaks piglit test fs-discard-exit-2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286530 91177308-0d34-0410-b5e6-96231b3b80d8

Fix requirements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286527 91177308-0d34-0410-b5e6-96231b3b80d8

ScheduleDAGInstrs: Ignore dependencies of constant physregs

There is no need to track dependencies for constant physregs, as they
don't change their value no matter in what order you read/write to them.

Differential Revision: https://reviews.llvm.org/D26221

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286526 91177308-0d34-0410-b5e6-96231b3b80d8

Timer: Remove group-less NamedRegionTimer constructor.

The NamedRegionTimer initializer without a group name puts the Timer
into the "Misc" group and is (nearly) unused. Remove it.

The only user of this constructor appears to be the HexagonGenInsert pass,
which creates a counter without group to count the complete execution
time of that pass, however since every pass gets a counter by the
PassManager anyway this should be unnecessary. Also removed the
pointless TimerGroup there.

Differential Revision: https://reviews.llvm.org/D25582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286524 91177308-0d34-0410-b5e6-96231b3b80d8

[DAG Combiner] Fix the native computation of the Newton series for reciprocals

The generic infrastructure to compute the Newton series for reciprocal and
reciprocal square root was conceived to allow a target to compute the series
itself.  However, the original code did not properly consider this condition
if returned by a target.  This patch addresses the issues to allow a target
to compute the series on its own.

Differential revision: https://reviews.llvm.org/D22975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286523 91177308-0d34-0410-b5e6-96231b3b80d8

GlobalISel: fix mistaken comment change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286517 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286516 91177308-0d34-0410-b5e6-96231b3b80d8

[LSR] Tweak loop-strength-reduce-crash test.  Test-only change.

Run opt instead of llc, and update the comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286515 91177308-0d34-0410-b5e6-96231b3b80d8

IR: Introduce inrange attribute on getelementptr indices.

If the inrange keyword is present before any index, loading from or
storing to any pointer derived from the getelementptr has undefined
behavior if the load or store would access memory outside of the bounds of
the element selected by the index marked as inrange.

This can be used, e.g. for alias analysis or to split globals at element
boundaries where beneficial.

As previously proposed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-July/102472.html

Differential Revision: https://reviews.llvm.org/D22793

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286514 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Updated knownbits vector ADD/SUB test

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286513 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector ADD test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286511 91177308-0d34-0410-b5e6-96231b3b80d8

ScheduleDAGInstrs: Slightly simplify code; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286510 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for splatted vectors in SUB opcode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286509 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector SUB test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286508 91177308-0d34-0410-b5e6-96231b3b80d8

RegisterCoalescer: Ignore interferences for constant physregs

When copying to/from a constant register interferences can be ignored.

Also update the documentation for isConstantPhysReg() to make it more
obvious that this transformation is valid.

Differential Revision: https://reviews.llvm.org/D26106

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286503 91177308-0d34-0410-b5e6-96231b3b80d8

AMDGPU: Emit runtime metadata as a note element in .note section

Currently runtime metadata is emitted as an ELF section with name .AMDGPU.runtime_metadata.

However there is a standard way to convey vendor specific information about how to run an ELF binary, which is called vendor-specific note element (http://www.netbsd.org/docs/kernel/elf-notes.html).

This patch lets AMDGPU backend emits runtime metadata as a note element in .note section.

Differential Revision: https://reviews.llvm.org/D25781

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286502 91177308-0d34-0410-b5e6-96231b3b80d8

Fix type ambiguity with std::max

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286498 91177308-0d34-0410-b5e6-96231b3b80d8

Fix initialization order error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286497 91177308-0d34-0410-b5e6-96231b3b80d8

[Support] Improve flexibility of binary blob formatter.

This makes it possible to indent a binary blob by a certain
number of bytes, and also makes some things more idiomatic.
Finally, it integrates this binary blob formatter into ScopedPrinter
which used to have its own implementation of this algorithm.

Differential Revision: https://reviews.llvm.org/D26477

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286495 91177308-0d34-0410-b5e6-96231b3b80d8

[PDB] Begin adding documentation for the PDB file format.

Differential Revision: https://reviews.llvm.org/D26374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286491 91177308-0d34-0410-b5e6-96231b3b80d8

[opt-viewer] Avoid duplicated remarks

This can happen if a pass is run multiple times or if the code is in a
header file which is included multiple times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286489 91177308-0d34-0410-b5e6-96231b3b80d8

[Target] Rename X86/ARM Assembly printer to reflect reality.

This shows up a lot profiling LTO testcases with -time-passes, so
better have a non confusing name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286488 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some Clang-tidy modernize-use-default and readability-redundant-member-init and Include What You Use warnings; other minor fixes.

Differential revision: https://reviews.llvm.org/D26087

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286484 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r286437 r286438, they caused PR30976

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286483 91177308-0d34-0410-b5e6-96231b3b80d8

[OptDiag] Remove non-printable chars from function name

The r283656 did this in the remark arguments.  We also need to do this
in the main function attribute as that is written to YAML as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286482 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286481 91177308-0d34-0410-b5e6-96231b3b80d8

Add comments about why we put LoopSink pass at the very late stage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286480 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector TRUNC test

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286477 91177308-0d34-0410-b5e6-96231b3b80d8

Restore part of "[ThinLTO] Prevent exporting of locals used/defined in module level asm"

This restores the part of r286297 that didn't require adding a
dependency from the Analysis to Object library. There are two parts
to the original fix, and this will address the handling for the case
where locals are used in module level asm.

The part that requires functionality in libObject handles local defs
in module level asm, and was reverted because our downstream build
of clang builds lib/Bitcode into a single library, and this new
dependency introduced a cycle there. I am trying to get that fixed
(see D26502), so for now that change isn't being restored

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286475 91177308-0d34-0410-b5e6-96231b3b80d8

Use common SDLoc. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286473 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in MUL opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286471 91177308-0d34-0410-b5e6-96231b3b80d8

reproducer for pr29002

https://reviews.llvm.org/D26449

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286470 91177308-0d34-0410-b5e6-96231b3b80d8

AMDGPU: Add VI i16 support

Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286464 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector MUL test

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286463 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in SRA opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286461 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] auto-generate better checks; NFC

Note that the existing metadata checking was re-added by hand because the
script doesn't currently know how to generate checks for lines outside of
functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286460 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector arithmetic shift test

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286457 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodes

We were failing to extract a constant splat shift value if the shifted value was being masked.

The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286454 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unnecessary check prefix directives. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286453 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL

Fails to match constant shift value due to presence of AND mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286452 91177308-0d34-0410-b5e6-96231b3b80d8

[RegionInfo] Add three tests that include infinite loops

These examples are variations that were inspired from a small subgraph taken
from paper.ll which are interesting as they show certain issues with infinite
loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286450 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286448 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add knownbits vector logical shift test

In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286447 91177308-0d34-0410-b5e6-96231b3b80d8

[ARM] Thumb2 LDR (literal) should accept PC as the destination

The version of this instruction with the .w suffix already correctly accepts
this, but the alias without the .w did not.

Differential Revision: https://reviews.llvm.org/D26499

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286446 91177308-0d34-0410-b5e6-96231b3b80d8

[SCEVExpander] Hoist unsigned divisons when safe

That is, when the divisor is a constant non-zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286438 91177308-0d34-0410-b5e6-96231b3b80d8

[SCEVExpander] Don't hoist divisions

Fixes PR30942.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286437 91177308-0d34-0410-b5e6-96231b3b80d8

Lift out a helper lambda; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286436 91177308-0d34-0410-b5e6-96231b3b80d8

[AVX-512] Allow legacy cvtpd2dq intrinsics to select EVEX encoded instruction when available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286435 91177308-0d34-0410-b5e6-96231b3b80d8

[AVX-512][X86] Convert avx_cvtt_ps2dq_256 and sse2_cvttps2dq intrinsics to ISD::FP_TO_SINT in the intrinsics table and delete patterns. While nearby also move CVTDQ2PS patterns into their instructions.

This allows these intrinsics to also use EVEX instructons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286434 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Convert int_x86_avx_cvtt_pd2dq_256 to fp_to_sint using the intrinsics table. Removes extra patterns and allows legacy intrinsic to select EVEX encoded instructions when available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286433 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Move some custom patterns into the currently empty pattern of their corresponding instructions. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286432 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove some patterns still referencing int_x86_sse2_cvttpd2dq that should have been removed in r286344. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286431 91177308-0d34-0410-b5e6-96231b3b80d8

[SCEV] Eta reduce some lambdas; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286429 91177308-0d34-0410-b5e6-96231b3b80d8

[LangRef] Drop "experimental" caveat from operand bundles

I think we're past that point now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286428 91177308-0d34-0410-b5e6-96231b3b80d8

[AVX-512] Add test cases to show missed opportunities for using VALIGND/Q to handle shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286425 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] avoid infinite loop from shuffle-extract-insert sequence (PR30923)

Removing the limitation in visitInsertElementInst() causes several regressions
because we're not prepared to fold sequences of shuffles or inserts and extracts
separated by shuffles. Fixing that appears to be a difficult mission because we
are purposely trying to avoid creating shuffles with arbitrary shuffle masks
because some targets may choke on those.

https://llvm.org/bugs/show_bug.cgi?id=30923

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286423 91177308-0d34-0410-b5e6-96231b3b80d8

Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable immediate.", with a fix for 32-bit x86.

Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions
that take a global address operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286420 91177308-0d34-0410-b5e6-96231b3b80d8

[AVR] Add a selection of CodeGen tests

Summary: This adds all of the CodeGen tests which currently pass.

Reviewers: arsenm, kparzysz

Subscribers: japaric, wdng

Differential Revision: https://reviews.llvm.org/D26388

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286418 91177308-0d34-0410-b5e6-96231b3b80d8

[AVR] Add all of the machine code test suite

Summary: This adds all of the AVR machine code tests.

Reviewers: arsenm, kparzysz

Subscribers: wdng, japaric

Differential Revision: https://reviews.llvm.org/D26387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286417 91177308-0d34-0410-b5e6-96231b3b80d8

Add isHotBB helper function to ProfileSummaryInfo

Summary: This will unify all BB hotness checks.

Reviewers: eraman, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26353

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286415 91177308-0d34-0410-b5e6-96231b3b80d8

Preserve assumption cache in loop-rotate.

No testcase included because I can't figure out how to reduce it.
(It's easy to write a testcase where rotation clones an assume,
but that doesn't actually seem to trigger the crash in opt on
its own; maybe an issue with the laziness?)

Differential Revision: https://reviews.llvm.org/D26434

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286410 91177308-0d34-0410-b5e6-96231b3b80d8

GlobalISel: fix typo. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286408 91177308-0d34-0410-b5e6-96231b3b80d8

GlobalISel: translate invoke and landingpad instructions

Pretty bare-bones support for exception handling (no weird MSVC stuff, no SjLj
etc), but it should get things going.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286407 91177308-0d34-0410-b5e6-96231b3b80d8

Update vectorization debug info unittest.

Summary:
The change will test the change in r286159.
The idea behind the change: Make the dbg location different between loop header and preheader/exit. Originally, dbg location 21 exists in 3 BBs: preheader, header, critical edge (exit). Update the debug location of inside the loop header from !21 to !22 so that it will reflect the correct location.

Reviewers: probinson

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26428

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286403 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] regenerate checks; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286402 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] regenerate checks; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286399 91177308-0d34-0410-b5e6-96231b3b80d8