Vikram S. Adve [Sat, 31 May 2003 07:37:05 +0000 (07:37 +0000)]
Changes to allow explicit physical register arguments that have been
preallocated. While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.
Vikram S. Adve [Sat, 31 May 2003 07:34:57 +0000 (07:34 +0000)]
Several bug fixes: globals in call operands were not being pulled out;
globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.
Vikram S. Adve [Sat, 31 May 2003 07:32:01 +0000 (07:32 +0000)]
Extensive changes to the way code generation occurs for function
call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
Misha Brukman [Sat, 31 May 2003 06:25:19 +0000 (06:25 +0000)]
The 'rd' register is consistently mentioned last in instruction definitions.
Created new classes from which instructions inherit their ordering of fields.
Misha Brukman [Fri, 30 May 2003 20:11:56 +0000 (20:11 +0000)]
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.
Code beautification for the rest of the code: changed layout to match the rest
of the code base.
Chris Lattner [Fri, 30 May 2003 19:22:14 +0000 (19:22 +0000)]
Okay totally give up on trying to optimize aggregates that cannot be completely
broken up into their elements. Too many programs break because of this.
Misha Brukman [Fri, 30 May 2003 18:06:10 +0000 (18:06 +0000)]
Because the format of the shift instructions is `shift r, shcnt, r', the
instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.
Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.
The other changes are just elimination of unnecessary spaces.
Tanya Lattner [Fri, 30 May 2003 15:50:18 +0000 (15:50 +0000)]
Added the CloneTrace function which clones traces. It takes a vector of basic blocks, removes
internal phi nodes, and returns a new vector of basic blocks.
Brian Gaeke [Fri, 30 May 2003 08:02:14 +0000 (08:02 +0000)]
Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
their fields were totally screwed up. This seems to fix the problem.
John Criswell [Thu, 29 May 2003 18:51:11 +0000 (18:51 +0000)]
Moved the FLEX and BISON macros from Makefile.common since they are
configuration options like CC and CXX.
Updated LLVMGCCDIR so that it refers to the valid LLVM gcc code.
Added pathnames and flags to be used by some of the tests.
Moved configuration options from Makefile.common to here since they
should all be in one place.
Misha Brukman [Thu, 29 May 2003 05:29:22 +0000 (05:29 +0000)]
When TableGen finds an error in the SparcV9.td file, it exits with a non-zero
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.
Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.
Misha Brukman [Thu, 29 May 2003 03:31:43 +0000 (03:31 +0000)]
* Broke up SparcV9.td into separate files as it was getting unmanageable
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr
Misha Brukman [Wed, 28 May 2003 17:49:29 +0000 (17:49 +0000)]
Fixed ordering of elements in instructions: although the binary instructions
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.
Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.
Vikram S. Adve [Wed, 28 May 2003 13:54:41 +0000 (13:54 +0000)]
Three kinds of boolean values handled incorrectly:
-- setCC of FP type used by a Phi: have to save in reg.
-- setNE of FP type used by a branch: cannot use result directly in branch!
-- setCC used outside the same basic block: have to save in reg. for now
Misha Brukman [Tue, 27 May 2003 22:43:19 +0000 (22:43 +0000)]
Added a debugging code emitter that prints code to a file, debug to std::cerr,
and passes the real code to a memory-outputting code emitter. This may be
removed at a later point in development.
Misha Brukman [Tue, 27 May 2003 22:39:01 +0000 (22:39 +0000)]
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.
Misha Brukman [Tue, 27 May 2003 22:37:00 +0000 (22:37 +0000)]
Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.
Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.
This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.
Misha Brukman [Tue, 27 May 2003 22:32:38 +0000 (22:32 +0000)]
One of the first major changes to make the work of JITting easier: adding
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.
This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.
As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.
Misha Brukman [Tue, 27 May 2003 22:24:48 +0000 (22:24 +0000)]
* Allow passing in an unsigned configuration to allocateSparcTargetMachine()
a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes
Misha Brukman [Tue, 27 May 2003 22:19:58 +0000 (22:19 +0000)]
* Now outputting a static function getBinaryCodeForInstr() (JIT-accessible)
* For debugging purposes:
+ output the predefined bit pattern of the instruction
* Fixed inefficiency: only load an operand from MachineInstr once
* Bug fix: did not advance bit index when seeing named bit-fields "annul", "cc"
and "predict"
* Added a catch-all for non-supported instructions at the end of switch stmt.
Misha Brukman [Tue, 27 May 2003 22:01:10 +0000 (22:01 +0000)]
Add prototypes to add passes to JIT compilation and code emission.
Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.
Misha Brukman [Tue, 27 May 2003 21:45:05 +0000 (21:45 +0000)]
Broke out class definition from SparcV9CodeEmitter, and added ability to take a
MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.
Misha Brukman [Tue, 27 May 2003 21:42:05 +0000 (21:42 +0000)]
Link in Sparc libs for the JIT, even on X86 to be able to support debugging
of Sparc JIT (printing out instrs) on X86. Con: this increases linking time.
Misha Brukman [Tue, 27 May 2003 21:40:39 +0000 (21:40 +0000)]
Allow for specification of which JIT to run on the commandline.
`lli -march=x86' or `lli -march=sparc' will forcefully select the JIT even on a
different platform. Running lli without the -march option will select the JIT
for the platform that it's currently running on.
Pro: can test Sparc JIT (debug printing mode) on X86 -- faster to compile/link
LLVM source base to test changes.
Con: Linking lli on x86 now pulls in all the Sparc libs -> longer link time
(but X86 can bear it, right?)
In the future, perhaps this should be a ./configure option to enable/disable
target JITting...
Misha Brukman [Tue, 27 May 2003 20:07:58 +0000 (20:07 +0000)]
SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main function
that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).
Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .
projects / llvm / log