Added functions cross-reference test.
Originally this similar was initiated by Björn Steinbrink here:
http://reviews.llvm.org/D3437
Bug itself has been fixed by principal changes in MergeFunctions. Though
special checks for functions merging are still actual. And the test has
been accepted with slight modifications.
Alp Toker [Mon, 9 Jun 2014 18:28:53 +0000 (18:28 +0000)]
Fold FEnv.h into the implementation
Support headers shouldn't use config.h definitions, and they should never be
undefined like this.
ConstantFolding.cpp was the only user of this facility and already includes
config.h for other math features, so it makes sense to move the checks there at
point of use.
(The implicit config.h was also quite dangerous -- removing the FEnv.h include
would have silently disabled math constant folding without causing any tests to
fail. Need to investigate -Wundef once the cleanup is done.)
This eliminates the last config.h include from LLVM headers, paving the way for
more consistent configuration checks.
[X86] Add target combine rules for horizontal add/sub.
This patch adds new target specific combine rules to identify horizontal
add/sub idioms from BUILD_VECTOR dag nodes.
This patch also teaches the DAGCombiner how to canonicalize sequences of
insert_vector_elt dag nodes according to the following rule:
(insert_vector_elt (insert_vector_elt A, I0), I1) ->
(insert_vecto_elt (insert_vector_elt A, I1), I0)
This new canonicalization rule only triggers if the inner insert_vector
dag node has exactly one use; also, both indices must be known constants,
and I1 < I0.
This last rule made it possible to write a simpler algorithm to identify
horizontal add/sub patterns because now we don't have to worry about the
ordering of insert_vector_elt dag nodes.
Bill Schmidt [Mon, 9 Jun 2014 16:06:29 +0000 (16:06 +0000)]
[PPC64LE] Generate correct little-endian code for v16i8 multiply
The existing code in PPCTargetLowering::LowerMUL() for multiplying two
v16i8 values assumes that vector elements are numbered in big-endian
order. For little-endian targets, the vector element numbering is
reversed, but the vmuleub, vmuloub, and vperm instructions still
assume big-endian numbering. To account for this, we must adjust the
permute control vector and reverse the order of the input registers on
the vperm instruction.
The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed
on powerpc64 and powerpc64le targets as well as the original powerpc
(32-bit) target.
[X86] Avoid emitting unnecessary test instructions.
This patch teaches the backend how to check for the 'NoSignedWrap' flag on
binary operations to improve the emission of 'test' instructions.
If the result of a binary operation is known not to overflow we know that
resetting the Overflow flag is unnecessary and so we can avoid emitting
the test instruction.
[DAG] Expose NoSignedWrap, NoUnsignedWrap and Exact flags to SelectionDAG.
This patch modifies SelectionDAGBuilder to construct SDNodes with associated
NoSignedWrap, NoUnsignedWrap and Exact flags coming from IR BinaryOperator
instructions.
Added a new SDNode type called 'BinaryWithFlagsSDNode' to allow accessing
nsw/nuw/exact flags during codegen.
Alexey Volkov [Mon, 9 Jun 2014 11:40:41 +0000 (11:40 +0000)]
[X86] Use ADD/SUB instead of INC/DEC for Silvermont
According to Intel Software Optimization Manual
on Silvermont INC or DEC instructions require
an additional uop to merge the flags.
As a result, a branch instruction depending
on an INC or a DEC instruction incurs a 1 cycle penalty.
Fix line numbers for code inlined from __nodebug__ functions.
Instructions from __nodebug__ functions don't have file:line
information even when inlined into no-nodebug functions. As a result,
intrinsics (SSE and other) from <*intrin.h> clang headers _never_
have file:line information.
With this change, an instruction without !dbg metadata gets one from
the call instruction when inlined.
Chad Rosier [Mon, 9 Jun 2014 01:25:51 +0000 (01:25 +0000)]
[AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
plus add. The shift can be folded into the add. This only effects codegen
when the constant is 3.
Jingyue Wu [Sun, 8 Jun 2014 23:49:34 +0000 (23:49 +0000)]
[SeparateConstOffsetFromGEP] inbounds zext => sext for better splitting
For each array index that is in the form of zext(a), convert it to sext(a)
if we can prove zext(a) <= max signed value of typeof(a). The conversion
helps to split zext(x + y) into sext(x) + sext(y).
David Blaikie [Sun, 8 Jun 2014 19:33:40 +0000 (19:33 +0000)]
SmallVector: Improve test coverage for insert with repetition
To test cases that involve actual repetition (> 1 elements), at least
one element before the insertion point, and some elements of the
original range that still fit in that range space after insertion.
Actually we need coverage for the inverse case too (where no elements
after the insertion point fit into the previously allocated space), but
this'll do for now, and I might end up rewriting bits of SmallVector to
avoid that special case anyway.
Tobias Grosser [Sun, 8 Jun 2014 19:21:20 +0000 (19:21 +0000)]
ScalarEvolution: Derive element size from the type of the loaded element
Before, we where looking at the size of the pointer type that specifies the
location from which to load the element. This did not make any sense at all.
This change fixes a bug in the delinearization where we failed to delinerize
certain load instructions.
X86Subtarget::isTargetCygMing || X86Subtarget::isTargetKnownWindowsMSVC is
equivalent to all Windows environments. Simplify the check to isOSWindows.
NFC.
David Blaikie [Sun, 8 Jun 2014 17:33:47 +0000 (17:33 +0000)]
SmallVectorTest: Remove some more robust checks added in r210429 since they caught some bugs I haven't fixed yet.
Specifically this caused inserting an element from a SmallVector into
itself when such an insertion would cause a reallocation. We have code
to handle this for non-reallocating cases, but it's not robust against
reallocation.
David Blaikie [Sun, 8 Jun 2014 16:55:13 +0000 (16:55 +0000)]
Fix some more moving-from-moved-from objects issues in SmallVector
(& because it makes it easier to test, this also improves
correctness/performance slightly by moving the last element in an insert
operation, rather than copying it)
Stephen Canon [Sun, 8 Jun 2014 16:53:31 +0000 (16:53 +0000)]
APFloat: x - NaN needs to flip the signbit of NaN when x is a number.
Because we don't have a separate negate( ) function, 0 - NaN does double-duty as the IEEE-754 negate( ) operation, which (unlike most FP ops) *does* attach semantic meaning to the signbit of NaN.
David Blaikie [Sun, 8 Jun 2014 16:18:35 +0000 (16:18 +0000)]
AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperand
I saw at least a memory leak or two from inspection (on probably
untested error paths) and r206991, which was the original inspiration
for this change.
I ran this idea by Jim Grosbach a few weeks ago & he was OK with it.
Since it's a basically mechanical patch that seemed sufficient - usual
post-commit review, revert, etc, as needed.
David Blaikie [Sun, 8 Jun 2014 16:00:02 +0000 (16:00 +0000)]
Ensure SmallVector::insert doesn't overwrite the last element in the range with the already-moved-from value
This would cause the last element in a range to be in a moved-from state
after an insert at a non-end position, losing that value entirely in the
process.
Side note: move_backward is subtle. It copies [A, B) to C-1 and down.
(the fact that it decrements both the second and third iterators before
the first movement is the subtle part... kind of surprising, anyway)
Alp Toker [Sun, 8 Jun 2014 09:13:42 +0000 (09:13 +0000)]
Revert "Do materialize for floating point"
1) The commit was made despite profound lack of understanding:
"I did not understand the comment about using dyn_cast instead of isa. I will
commit as is and make the update after. You can explain what you meant to me."
Commit first, understand later isn't OK.
2) Review comments were simply ignored:
"Can you edit the summary to describe what the patch is for? It appears to be
a list of commits at the moment."
3) The patch got LGTM'd off-list without any indication of readiness.
4) The public mailing list was excluded from patch review so all of this was
hidden from the community.
link.exe requires that the text section has the IMAGE_SCN_MEM_16BIT flag set.
Otherwise, it will treat the function as ARM. If this occurs, then jumps to the
function will fail, switching from thumb to ARM mode execution.
With this change, it is possible to link using the MSVC linker as well.
Reed Kotler [Sun, 8 Jun 2014 03:30:32 +0000 (03:30 +0000)]
Do materialize for floating point
Summary:
start to do simple constants
finish simplestore
add test case
format
Merge branch 'master' into 1756_8
Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel
Merge branch 'master' into 1756_8
Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel
in progress
finish integer materialize
test cases
test cases
in progress
Finish up fast-isel materialize for ints.
Finish materialize for ints
test cases
simplestorei.ll
Merge branch 'master' into 1756_8
fix fp constants for fast-isel
Merge branch '1758_1' of dmz-portal.mips.com:llvm into 1758_1
Reed Kotler [Sun, 8 Jun 2014 03:04:42 +0000 (03:04 +0000)]
start to clean up buildMI calls in mips fast-isel
Summary: Merge branch 'master' into 1758_6
Test Plan:
No functionality change. Run "make check" and run test-suite.
Because our servers are not yet running again I have not yet run test-suite.
I will further review myself before submission.
Rather than requiring ARM support for the ELF tests (which is odd), move the
tests that require ARM into a subdirectory to use lit to disable them if the
support is not present. Play this game to prevent disabling the ELF tests on
the Windows build bots as they have caught issues in the past with interactions
between various platforms.
MC: make ELF .type handling more GNU AS compatible
GAS documents the .type directive as having an optional comma following the key
symbol name when using the STT_<TYPE_IN_UPPER_CASE> form. However, it treats
the comma as optional in all cases. This makes the IAS support both forms of
inputs. Furthermore, the prefixed forms take either the upper case name or the
lower case alias.
The tests are split into two separate sets as the hash character serves as a
comment character on x86, which is tested in the second set by using arm-elf
which uses the at symbol as a comment character.
This adjusts the section setup for the windows-itanium environment. This
environment does not report to be a known windows msvc environment, even though
it is (nearly) identical to the MSVC environment for C code.
Add some whitespace, combine two sequential conditionals into a single one.
Reformat some section definitions to maintain uniformity in the function.
NFC.
Alp Toker [Sat, 7 Jun 2014 20:39:53 +0000 (20:39 +0000)]
Build fix: remove initializeJumpInstrTablesPass() call from LTO
This was incurring an unsatisfied dependency on CodeGen from LTO breaking
shared builds:
Undefined symbols for architecture x86_64:
"llvm::initializeJumpInstrTablesPass(llvm::PassRegistry&)", referenced from:
llvm::LTOCodeGenerator::initializeLTOPasses() in LTOCodeGenerator.cpp.o
ld: symbol(s) not found for architecture x86_64
clang: error: linker command failed with exit code 1 (use -v to see invocation)
Removed as a temporary measure pending feedback from the author.
COFF/PE, so the relocation model is never static. Loosen the assertion
accordingly. The relocation can still be emitted properly, as it will be
converted to an IMAGE_REL_ARM_ADDR32 which will be resolved by the loader
taking the base relocation into account. This is necessary to permit the
emission of long calls which can be controlled via the -mlong-calls option in
the driver.
tools: add a high level explanation for WoA EH data
Add a brief explanation of the data section layout for the unwind data that the
Windows on ARM EH models. This is simply to provide a rough idea of the layout
of the code involved in the decoding of the unwinding. Details on the involved
data structures are available in the associated support header. The bulk of it
is related to printing out the byte-code to help validate generation of WoA EH.
Andrew Trick [Sat, 7 Jun 2014 01:48:43 +0000 (01:48 +0000)]
Fix the MachineScheduler's logic for updating ready times for in-order.
Now the scheduler updates a node's ready time as soon as it is
scheduled, before releasing dependent nodes. There was a reason I
didn't do this initially but it no longer applies.
A53 is in-order and was running into an issue where nodes where added
to the readyQ too early. That's now fixed.
This also makes it easier for custom scheduling strategies to build
heuristics based on the actual cycles that the node was scheduled at.
The only impact on OOO (sandybridge/cyclone) is that ready times will
be slightly more accurate. I didn't measure any significant regressions.
Add an isWindowsItaniumEnvironment function to Triple to mirror the other
Windows environments. This is simply a utility function to check if we are
targeting windows-itanium rather than windows-msvc.
Prevent the early elimination of sections in the object writer. There may be
references to the section itself by other symbols, which may potentially not be
possible to resolve. ML (Visual Studio's Macro Assembler) also seems to retain
empty sections.
The elimination of symbols and sections which are unused should really occur at
the link phase. This will not cause any change in the resulting binary, simply
in the generated object files.
The adjustments to the other unit tests account for the fluctuating section
index caused by the appearance of sections which were previously discarded.
* Section association cannot use just the section name as many
sections can have the same name. With this patch, the comdat symbol in
an assoc section is interpreted to mean a symbol in the associated
section and the mapping is discovered from it.
* Comdat symbols were not being set correctly. Instead we were getting
whatever was output first for that section.
A consequence is that associative sections now must use .section to
set the association. Using .linkonce would not work since it is not
possible to change a sections comdat symbol (it is used to decide if
we should create a new section or reuse an existing one).
This includes r210298, which was reverted because it was asserting
on an associated section having the same comdat as the associated
section.
David Blaikie [Fri, 6 Jun 2014 18:45:14 +0000 (18:45 +0000)]
Match the full hex offsets in test/DebugInfo/X86/gnu-public-names.ll
These checks were accidentally skipping the 0x prefix in the hex
offsets, then cunningly ignoring the prefix in the use of those captured
values.
Except in the case of the unit length, where the match was only matching
the leading '0' before the x in the 0x prefix, then matching that
against the length. We can't actually express the length association
here, as the length field in the Compile Unit header does not include
the length field itself, but the length field in the pubnames section
/does/ include the size of the length field in the Compile Unit header -
so the two numbers are actually 4 bytes different. Just skip matching
that.
David Blaikie [Fri, 6 Jun 2014 18:22:04 +0000 (18:22 +0000)]
Remove DWARF3 testing of test/DebugInfo/X86/gnu-public-names.ll
This was added to test that DW_AT_GNU_pubnames used sec_offset in DWARF4
and data4 in DWARF3 and below. Since then we've updated
DW_AT_GNU_pubnames to be a flag, rather than a section offset anyway.
Granted this still differs between DWARF 3 and DWARF 4
(FORM_flag_present versun FORM_flag) but it doesn't seem worthwhile
testing that codepath again here. It's covered adequately in many other
test cases.
And while I'm here, don't hardcode the byte size of the compile unit -
it's not relevant to this test and just makes it brittle if/when
anything changes in the way this CU is emitted.
Bill Schmidt [Fri, 6 Jun 2014 14:06:26 +0000 (14:06 +0000)]
[PPC64LE] Fix lowering of BUILD_VECTOR and SHUFFLE_VECTOR for little endian
This patch fixes a couple of lowering issues for little endian
PowerPC. The code for lowering BUILD_VECTOR contains a number of
optimizations that are only valid for big endian. For now, we disable
those optimizations for correctness. In the future, we will add
analogous optimizations that are correct for little endian.
When lowering a SHUFFLE_VECTOR to a VPERM operation, we again need to
make the now-familiar transformation of swapping the input operands
and complementing the permute control vector. Correctness of this
transformation is tested by the accompanying test case.
Karthik Bhat [Fri, 6 Jun 2014 06:20:08 +0000 (06:20 +0000)]
Fix PR19657 (scalar loads not combined into vector load)
If we have common uses on separate paths in the tree; process the one with greater common depth first.
This makes sure that we do not assume we need to extract a load when it is actually going to be part of a vectorized tree.
Alp Toker [Fri, 6 Jun 2014 05:08:42 +0000 (05:08 +0000)]
Remove clang-specific libxml2 check from CMake
clang's own CMake setup handles this as of r210308.
The CMAKE_CROSSCOMPILING special-case will no longer be hard-coded. This was
clearly site-specific to someone's local configuration and should be passed in
at configure time if needed with e.g. -DLIBXML2_LIBRARIES=... (the libxml2
target I tried here doesn't even support liblzma so it's *way* off).
Alias with unnamed_addr were in a strange state. It is stored in GlobalValue,
the language reference talks about "unnamed_addr aliases" but the verifier
was rejecting them.
It seems natural to allow unnamed_addr in aliases:
* It is a property of how it is accessed, not of the data itself.
* It is perfectly possible to write code that depends on the address
of an alias.
This patch then makes unname_addr legal for aliases. One side effect is that
the syntax changes for a corner case: In globals, unnamed_addr is now printed
before the address space.
We extended the .section syntax to allow multiple sections with the
same name but different comdats, but currently we don't make sure that
the output section has that comdat symbol.
That happens to work with the code llc produces currently because it looks like
Bill Schmidt [Thu, 5 Jun 2014 22:57:38 +0000 (22:57 +0000)]
[PPC64LE] Add test case for r210282 commit
Chandler correctly pointed out that I need an LLVM IR test for
r210282, which modified the vperm -> shuffle transform for little
endian PowerPC. This patch provides that test.
Remove X86Subtarget from the X86FrameLowering constructor since
we can just pass in the values we already know and we're not
caching the subtarget anymore.
projects / llvm / log