Merge branch 'bugfix/tw7105_tcp_stable_test_abort_issue' into 'master'
lwip: fix tcp stable test abort issue
This MR covers following changes:
1. Modify dhcp server timer to 1 seconds
2. Enable ETHARP_TRUST_IP_MAC. Consider following scenario: we are in throughput test or traffic stability test, if this option is disabled, then every 5 minutes, the IP/MAC entry in arch cache is aged out, however, the traffic continuously send to lwip from application, because there is no IP/MAC entry in ARP cache, then the packets have to be buffered in ARP queue and a ARP request is triggered, but the ARP queue can only holds 3 packets, the later packets will be dropped, then if the traffic is big, a lot of packets will be dropped here before we get the right ARP response. For TCP, this will trigger re-transmit, it's intolerable for some application, such as real time audio, if re-transmit happen, then performance of voice will be impact. For UDP, sometimes it may also cause problem, such as DHCP, if here we failed to send the DHCP here, we has to wait the DHCP timeout etc... so this option is enabled here by default.
Merge branch 'feature/add_limit_for_all_dynamic_ebuf' into 'master'
esp32: update wifi lib for limitting dynamic wifi buffer
Add limit for all dynamic wifi ebuf to avoid wifi run out of memory in some extreme scanrio.
The default max allocated dynamic tx buffer is 32
The default max allocated dynamic rx buffer is 64, make default value is bigger because when all packets we received are small packets, e.g. the length is 64Bytes, then 64K can hold 1000 packets, so 64 maybe a good candidate default value, anyway the customer can configure it via menuconfig.
The default dynamic wifi internal long/long-long mgmt is 32, generally 32 is enough for mgmt packet (beacon/auth/assoc/probe/null etc). Generally when all the 32 mgmt buffer is run out of memory, it means internal wifi state machine may has problem, we need to debug it.
There are some RODATAs of libphy.a that are called in ISR. So need
to put them into DRAM to avoid access them when R/W SPI flash. Due
to the RODATAs which are called in ISR haven't been picked out to
put into DRAM, put all of the RODATA of libphy.a into DRAM. This
will be optimized in the future.
Ivan Grokhotkov [Fri, 21 Apr 2017 11:40:45 +0000 (19:40 +0800)]
Merge branch 'bugfix/rtc_reg_fields' into 'master'
soc: allow REG_SET_FIELD to be used for bit fields
- Fixes an issue with `rtc_clk_apll_enable`: https://esp32.com/viewtopic.php?f=13&t=1673
- Fixes `rtc_clk_fast_freq_set` function always selecting XTAL/4 as fast clock source.
- Fixes regression in deep sleep current (7uA instead of 5uA).
Ivan Grokhotkov [Fri, 21 Apr 2017 11:38:46 +0000 (19:38 +0800)]
Merge branch 'bugfix/xtal_freq_after_wdt_reset' into 'master'
rtc_clk_init: handle case when XTAL frequency has already been set
On first reset, ROM code writes the estimated XTAL frequency into
RTC_APB_FREQ_REG (aka STORE5). If the application doesn’t specify exact
XTAL frequency (which is always the case for now), rtc_clk_init will
guess what kind of XTAL is used (26M or 40M), based on the estimated
frequency. Later, detected frequency is written into RTC_XTAL_FREQ_REG
(aka STORE4).
When the application switches clock source to PLL, APB frequency changes
and RTC_APB_FREQ_REG is updated. If the application encounters an RTC
WDT reset, RTC_APB_FREQ_REG will not be updated prior to reset. Once the
application starts up again, it will attempt to auto-detect XTAL
frequency based on RTC_APB_FREQ_REG, which now has value of 80000000.
This will fail, and rtc_clk_xtal_freq_estimate will fall back to the
default value of 26 MHz. Due to an incorrect XTAL frequency, PLL
initialization will also take incorrect path, and PLL will run at a
different frequency. Depending on the application this may cause just
garbage output on UART or a crash (if WiFi is used).
This change checks if RTC_XTAL_FREQ_REG has already been set before trying
to estimate XTAL frequency based on the value of RTC_APB_FREQ_REG, and
uses RTC_XTAL_FREQ_REG value if it is valid.
Base MAC address can be stored in default manufacture-defined or customer
pre-defined place in EFUSE and other place e.g. flash or EEPROM.
If choose to use base MAC address which is stored in other place, please
call esp_base_mac_addr_set_external() before initializing WiFi/BT/Ehternet.
Merge branch 'bugfix/mbedtls_wrong_errno' into 'master'
mbedtls port: Fix detection of EWOULDBLOCK/EAGAIN with non-blocking sockets
Since mbedtls_net_errno is reset by fcntl, it is reset after calling
net_would_block, so the call to mbedtls_net_errno in mbedtls_net_recv
and mbedtls_net_send will always get back 0. This change propagates
the value returned by mbedtls_net_errno up through net_would_block,
to allow the correct error value to be used and avoid a redundant
call to mbedtls_net_errno.
Ivan Grokhotkov [Fri, 21 Apr 2017 02:33:58 +0000 (10:33 +0800)]
rtc_clk_init: handle case when XTAL frequency has already been set
On first reset, ROM code writes the estimated XTAL frequency into
RTC_APB_FREQ_REG (aka STORE5). If the application doesn’t specify exact
XTAL frequency (which is always the case for now), rtc_clk_init will
guess what kind of XTAL is used (26M or 40M), based on the estimated
frequency. Later, detected frequency is written into RTC_XTAL_FREQ_REG
(aka STORE4).
When the application switches clock source to PLL, APB frequency changes
and RTC_APB_FREQ_REG is updated. If the application encounters an RTC
WDT reset, RTC_APB_FREQ_REG will not be updated prior to reset. Once the
application starts up again, it will attempt to auto-detect XTAL
frequency based on RTC_APB_FREQ_REG, which now has value of 80000000.
This will fail, and rtc_clk_xtal_freq_estimate will fall back to the
default value of 26 MHz. Due to an incorrect XTAL frequency, PLL
initialization will also take incorrect path, and PLL will run at a
different frequency. Depending on the application this may cause just
garbage output on UART or a crash (if WiFi is used).
Make sure LD -L option is calculated correctly when the project Makefile has specified SRCDIRS components that are not directly below Makefile folder level.
For example,
SRCDIRS = comp_a happy/comp_b /c/dev/comp_c
Then the following are built:
build/comp_a/libcomp_a.a
build/comp_b/libcomp_b.a
build/comp_c/libcomp_c.a
But when LD is run the -L is calculated as follows
-L build/comp_a
-L build/happy/comp_b
-L build//c/dev/comp_c
This means comp_b and comp_c are not found by LD. With this change set -L is calculated correctly for comp_b and comp_c
Michael Kellner [Thu, 13 Apr 2017 18:11:13 +0000 (11:11 -0700)]
spidriver: Display length errors correctly
SPI transfer length is bits, not bytes, so the error should indicate bits. Also, there are separate lengths for rx and
tx (confusingly named rxlength and length... if rxlength is 0, length is used). The code checks the tx length for the
rx, so it never validates rxlength.
Originally contributed as part of #511 https://github.com/espressif/esp-idf/pull/511
Michael Kellner [Tue, 11 Apr 2017 20:08:35 +0000 (13:08 -0700)]
mbedtls port: Fix detection of EWOULDBLOCK/EAGAIN with non-blocking sockets
Since mbedtls_net_errno is reset by fcntl, it is reset after calling
net_would_block, so the call to mbedtls_net_errno in mbedtls_net_recv
and mbedtls_net_send will always get back 0. This change propagates
the value returned by mbedtls_net_errno up through net_would_block,
to allow the correct error value to be used and avoid a redundant
call to mbedtls_net_errno.
Merge branch 'bugfix/dont_log_before_bss_inited' into 'master'
Remove ESP_EARLY_LOGI before bss is initialized; it crashes the CPU
There's an ESP_EARLY_LOGI line that can get called before the BSS is initialized; the early logging code doesn't cope well with that: it checks if FreeRTOS is up, but the variables it uses for that contains garbage because it isn't cleared yet, giving the wrong result. The logging code then tries to set a mux, crashing the entire system. This patch removes the log line and adds a warning at the BSS initialization line not to do anything complex before that point.
Alexey Gerenkov [Wed, 25 Jan 2017 16:35:28 +0000 (19:35 +0300)]
esp32: Adds functionality for application tracing over JTAG
- Implements application tracing module which allows to send arbitrary
data to host over JTAG. This feature is useful for analyzing
program modules behavior, dumping run-time application data etc.
- Implements printf-like logging functions on top of apptrace module.
This feature is a kind of semihosted printf functionality with lower
overhead and impact on system behaviour as compared to standard printf.
spiflash ROM functions: Remove Quad I/O mode enable/disable code from flash ROM functions
Confusion here is that original ROM has two functions:
* SPIReadModeCnfig() - sets mode, calls enable_qio_mode/disable_qio_mode
* SPIMasterReadModeCnfig() - As above, but doesn't set QIO mode in status register
However we never want to use the ROM method to set/clear QIO mode flag, as not all flash chips work this way. Instead we
do it in flash_qio_mode.c in bootloader.
So in both cases (ROM or "patched ROM") we now call SPIMasterReadModeCnfig(), which is now named
esp_rom_spiflash_config_readmode().
Ivan Grokhotkov [Thu, 13 Apr 2017 07:29:09 +0000 (15:29 +0800)]
Merge branch 'bugfix/uart_tx_buffer_blocked' into 'master'
Fix uart tx function block issue
To enable tx empty interrupt each time the tx ringbuffer get filled, so that tx function will not block if tx data length is larger than tx ringbuffer size.
Reported from customer of Audio team.
Ivan Grokhotkov [Thu, 13 Apr 2017 07:27:37 +0000 (15:27 +0800)]
Merge branch 'bugfix/http_request_example' into 'master'
Fix issues with HTTP[S] request examples
This MR includes:
- request string fix for the http_request example (https://github.com/espressif/esp-idf/pull/500)
- same fix applied to the https_request example
- stack size increase for http_request example
The source branch "feature/btdm_avrc" includes classic Bluetooth profiles A2DP(sink role) and AVRCP(controller role);
Menuconfig options to control whether to enable classic BT is added.
Ivan Grokhotkov [Wed, 12 Apr 2017 13:30:07 +0000 (21:30 +0800)]
Merge branch 'bugfix/ota_runtime_check_encrypted_flash' into 'master'
Enable checks for encrypted flash in OTA
Even if firmware is compiled without CONFIG_FLASH_ENCRYPTION_ENABLED.
Rationale: CONFIG_FLASH_ENCRYPTION_ENABLED controls whether boot loader generates keys for encryption or not, but flash encryption can be configured externally. With this change, it's possible to have boot loader not generate keys but still have encryption working.
To enable tx empty interrupt each time the tx ringbuffer get filled, so that tx function will not block if tx data length is larger than tx ringbuffer size.
Reported from customer of Audio team.
Ivan Grokhotkov [Wed, 12 Apr 2017 02:39:22 +0000 (10:39 +0800)]
Merge branch 'bugfix/uart_rmt_fixes' into 'master'
Fixes for UART and RMT drivers
- Add const qualifier for config and tx data in RMT (https://github.com/espressif/esp-idf/pull/495)
- Fix rmt_set_tx_thr_intr_en(): check evt_thresh only in enable path (https://github.com/espressif/esp-idf/pull/492)
- Fix impossible check in uart_set_line_inverse (https://github.com/espressif/esp-idf/pull/489)
Ivan Grokhotkov [Wed, 12 Apr 2017 02:38:23 +0000 (10:38 +0800)]
Merge branch 'feature/rtc_clk_impl' into 'master'
Introduce soc component, add source of rtc_clk and rtc_pm libraries
This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.
Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.
Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.
Ivan Grokhotkov [Tue, 11 Apr 2017 12:09:06 +0000 (20:09 +0800)]
Merge branch 'bugfix/flash_busy_check_Wait_SPI_Idle' into 'master'
Bugfix/flash busy check wait spi idle
This branch moves some ROM SPI flash driver to IDF to fix bug in Wait_SPI_Idle() function.
Also it applies code style rules of IDF to integrated ROM driver sources.
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