The source branch "feature/btdm_avrc" includes classic Bluetooth profiles A2DP(sink role) and AVRCP(controller role);
Menuconfig options to control whether to enable classic BT is added.
Ivan Grokhotkov [Wed, 12 Apr 2017 13:30:07 +0000 (21:30 +0800)]
Merge branch 'bugfix/ota_runtime_check_encrypted_flash' into 'master'
Enable checks for encrypted flash in OTA
Even if firmware is compiled without CONFIG_FLASH_ENCRYPTION_ENABLED.
Rationale: CONFIG_FLASH_ENCRYPTION_ENABLED controls whether boot loader generates keys for encryption or not, but flash encryption can be configured externally. With this change, it's possible to have boot loader not generate keys but still have encryption working.
Ivan Grokhotkov [Wed, 12 Apr 2017 02:39:22 +0000 (10:39 +0800)]
Merge branch 'bugfix/uart_rmt_fixes' into 'master'
Fixes for UART and RMT drivers
- Add const qualifier for config and tx data in RMT (https://github.com/espressif/esp-idf/pull/495)
- Fix rmt_set_tx_thr_intr_en(): check evt_thresh only in enable path (https://github.com/espressif/esp-idf/pull/492)
- Fix impossible check in uart_set_line_inverse (https://github.com/espressif/esp-idf/pull/489)
Ivan Grokhotkov [Wed, 12 Apr 2017 02:38:23 +0000 (10:38 +0800)]
Merge branch 'feature/rtc_clk_impl' into 'master'
Introduce soc component, add source of rtc_clk and rtc_pm libraries
This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.
Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.
Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.
Ivan Grokhotkov [Tue, 11 Apr 2017 12:09:06 +0000 (20:09 +0800)]
Merge branch 'bugfix/flash_busy_check_Wait_SPI_Idle' into 'master'
Bugfix/flash busy check wait spi idle
This branch moves some ROM SPI flash driver to IDF to fix bug in Wait_SPI_Idle() function.
Also it applies code style rules of IDF to integrated ROM driver sources.
Deomid Ryabkov [Fri, 24 Mar 2017 16:17:15 +0000 (16:17 +0000)]
Enable checks for encrypted flash in OTA
Even if firmware is compiled without CONFIG_FLASH_ENCRYPTION_ENABLED
Rayionale: CONFIG_FLASH_ENCRYPTION_ENABLED controls whether boot loader
generates keys for encryption or not, but flash encryption can be
configured externally. With this change, it's possible to have boot
loader not generate keys but still have encryption working.
Alexey Gerenkov [Thu, 9 Mar 2017 07:29:00 +0000 (10:29 +0300)]
spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
Merge branch 'test/reboot_between_unit_test_cases' into 'release/v2.0'
CI: add reset between running each unit test cases
Unit test is designed to detect bug **within** each test case. Therefore we'll reset between each case to provide a clean context. We will later add stress cases to run unit test cases together to detect potential bugs.
Ivan Grokhotkov [Wed, 5 Apr 2017 12:52:13 +0000 (20:52 +0800)]
Merge branch 'test/reboot_between_unit_test_cases' into 'release/v2.0'
CI: add reset between running each unit test cases
Unit test is designed to detect bug **within** each test case. Therefore we'll reset between each case to provide a clean context. We will later add stress cases to run unit test cases together to detect potential bugs.
Ivan Grokhotkov [Mon, 10 Apr 2017 04:19:35 +0000 (12:19 +0800)]
Merge branch 'feature/ci_check_commits' into 'master'
CI: check if commit history need revise
Usually we need to cleanup the commit history before MR merged. Sometime we forget to squash before merge.
We can add certain pattern at the beginning of commit message, and add a job in deploy stage to check the patterns.
When we want to push code for review or resolve review comments, we can add this pattern to commit message as a reminder.
This will not block CI tests, checking job will always be put in the last CI stage.
Ivan Grokhotkov [Mon, 10 Apr 2017 04:19:10 +0000 (12:19 +0800)]
Merge branch 'bugfix/cross_core_int_init_single_core' into 'master'
esp32: initialize cross-core interrupt in single core mode
The software interrupt originally used as the cross-core interrupt is
now also used to yield from a FreeRTOS critical section; therefore it
must be initialized for single core mode as well.
Ivan Grokhotkov [Mon, 10 Apr 2017 04:18:47 +0000 (12:18 +0800)]
Merge branch 'bugfix/esp_error_check_release_builds' into 'master'
fix warnings generated by ESP_ERROR_CHECK(variable) in release builds
This uses the same pattern as “assert” in release builds to silence the
warning. At the same time, we make sure that if a statement is wrapped
into ESP_ERROR_CHECK, it is executed in release build as well.
chenyudong [Mon, 20 Mar 2017 05:43:04 +0000 (13:43 +0800)]
tcp_perf:modify tcp_perf with some new options.
You can set esp32 as AP/STA, client/sever, sender/recever in menuconfig.
You can set whether to display delay time info in menuconfig.
Now you can transfer data between esp and esp.
Ivan Grokhotkov [Fri, 7 Apr 2017 07:24:58 +0000 (15:24 +0800)]
fix warnings generated by ESP_ERROR_CHECK(variable) in release builds
This uses the same pattern as “assert” in release builds to silence the
warning. At the same time, we make sure that if a statement is wrapped
into ESP_ERROR_CHECK, it is executed in release build as well.
Ivan Grokhotkov [Fri, 7 Apr 2017 06:48:08 +0000 (14:48 +0800)]
esp32: initialize cross-core interrupt in single core mode
The software interrupt originally used as the cross-core interrupt is
now also used to yield from a FreeRTOS critical section; therefore it
must be initialized for single core mode as well.
Ivan Grokhotkov [Fri, 7 Apr 2017 04:13:42 +0000 (12:13 +0800)]
Merge branch 'feature/btdm_uart_hci' into 'master'
Feature/btdm uart hci
1. support UART HCI, devolper need not to make a bridge between VHCI and UART.
2. fix bug of rand/srand called in ISR.
3. fix bug of BLE rx packets may cause assert.
Tian Hao [Fri, 24 Mar 2017 06:57:07 +0000 (14:57 +0800)]
component/bt : support UART HCI and fix some bugs
1. support UART HCI, devolper need not to make a bridge between VHCI and UART.
2. fix bug of rand/srand called in ISR.
3. fix bug of BLE rx packets may cause assert.
Ivan Grokhotkov [Fri, 31 Mar 2017 08:02:26 +0000 (16:02 +0800)]
Merge branch 'bugfix/flash_op_deadlock' into 'master'
spi_flash: fix race condition in s_flash_op_complete access
Flash operation complete flag was cleared by the CPU initiating flash operation. If the other core was running an ISR, then IPC task could be late to enter the loop to check `s_flash_op_complete` by the time next flash operation started. This would cause a deadlock, as the IPC task would still be waiting for `s_flash_op_complete` to be set (which was already cleared by the next flash operation), while the flash operation task would be blocked waiting for IPC task to set `s_flash_op_can_start`.
If the flag is cleared on the CPU waiting on this flag, then the race condition can not happen.
Jeroen Domburg [Fri, 31 Mar 2017 02:44:37 +0000 (10:44 +0800)]
Merge branch 'bugfix/spi_timing_issues' into 'master'
Fix timing adjustment needed for higher speeds of SPI master bus.
Ref https://github.com/espressif/esp-idf/issues/363 . It was found out the master SPI driver didn't exactly calculate the delay compensation needed, breaking 20 and 26MHz full-duplex mode. This fixes these use cases. We also found out 40MHz full-duplex routed over the GPIO matrix does not work because of a hardware quirk; this MR adds a check/error for that case until we find a workaround.
Ivan Grokhotkov [Wed, 29 Mar 2017 09:37:34 +0000 (17:37 +0800)]
Merge branch 'bugfix/git_porcelain_arg' into 'master'
make: remove version parameter from git status porcelain option
Version parameter was added in git 2.11, while default git on macOS is
currently 2.10. According to the latest git docs, if the version
parameter is not provided, it defaults to ‘v1’, so removing it doesn’t
change the format.
Angus Gratton [Wed, 29 Mar 2017 00:50:49 +0000 (08:50 +0800)]
Merge branch 'bugfix/example_naming' into 'master'
examples: Standardise naming of files, symbols, etc. in examples
* Use "example" in all example function & variable names,
ie use i2c_example_xxx instead of i2c_xxx for example functions.
Closes #198 https://github.com/espressif/esp-idf/issues/198
* Mark example functions, etc. static
* Replace uses of "test" & "demo" with "example"
* Split the UART example into two
* Rename "main" example files to end with "_main.c" for disambiguation
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