Martin Storsjo [Fri, 3 Nov 2017 07:18:21 +0000 (07:18 +0000)]
[llvm-nm] Don't error out on multiple occurrances of the -g/--external-only flag
GNU binutils nm doesn't error out on this, and some projects' build
systems can end up doing that in some cases. Allowing that seems like
a better target than trying to avoid user projects passing multiple
-g parameters to $NM.
Martin Storsjo [Fri, 3 Nov 2017 07:18:14 +0000 (07:18 +0000)]
[llvm-nm] Print 'I' for import table data in COFF
The character gets uppercased into 'I' when it's a global symbol.
In GNU binutils, nm prints 'I' for symbols classified by
bfd_is_ind_section - which probably isn't exactly/only import
tables.
When building for win32, (some incarnations of?) libtool has got
rules that try to inspect linked libraries, and in order to
be sure that it is linking to a DLL import library as opposed to
a static library, it expects to find the string " I " in the output
of $NM when run on such an import library.
GNU binutils nm also flags all of the .idata$X chunks as 'i' (while
this patch only makes it set on .idata$2 and .idata$6) and also
flags __imp__function as 'I'.
Craig Topper [Fri, 3 Nov 2017 06:48:02 +0000 (06:48 +0000)]
[X86] Remove PALIGNR/VALIGN handling from combineBitcastForMaskedOp and move to isel patterns instead. Prefer 128-bit VALIGND/VALIGNQ over PALIGNR during lowering when possible.
Jake Ehrlich [Thu, 2 Nov 2017 23:45:51 +0000 (23:45 +0000)]
Reland "Add feature to determine if host architecture is 64-bit in llvm-lit"
A member of config was removed in this patch which resulted in errors I
didn't expect. Removing config.host_arch will take more work some I'm
readding that field.
[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.
This fixes http://llvm.org/PR32560. We were missing a description for
half floating point type and as a result were using the FPR 32 mapping.
Because of the size mismatch the generic code was complaining that the
default mapping is not appropriate. Fix the mapping description so that
the default mapping can be properly applied.
Puyan Lotfi [Thu, 2 Nov 2017 23:37:32 +0000 (23:37 +0000)]
mir-canon: First commit.
mir-canon (MIRCanonicalizerPass) is a pass designed to reorder instructions and
rename operands so that two similar programs will diff more cleanly after being
run through mir-canon than they would otherwise. This project is still a work
in progress and there are ideas still being discussed for improving diff
quality.
M include/llvm/InitializePasses.h
M lib/CodeGen/CMakeLists.txt
M lib/CodeGen/CodeGen.cpp
A lib/CodeGen/MIRCanonicalizerPass.cpp
Jake Ehrlich [Thu, 2 Nov 2017 23:24:04 +0000 (23:24 +0000)]
[llvm-objcopy] Fix bug in how segment alignment was being handled
Just aligning segment offsets to segment alignment is incorrect and also
wastes more space than is needed. The requirement is that p_offset ==
p_addr modulo p_align *not* that p_offset == 0 modulo p_align. Generally
speaking we've been using p_addr == 0 modulo p_align. In fact yaml2obj
can't even produce a valid situation which causes llvm-objcopy to
produce incorrect results because alignment and offset were both
inherited from the sections the program header covers. This change fixes
this bad behavior in llvm-objcopy.
Jake Ehrlich [Thu, 2 Nov 2017 23:14:55 +0000 (23:14 +0000)]
Add feature to determine if host architecture is 64-bit in llvm-lit
I have a test that I'd like to add to llvm that demands using more than
32-bits worth of address space. This test can't be run on 32-bit systems
because they don't have enough address space. The host triple should be
used to determine this instead of config.host_arch because on Debian
systems config.host_arch is not correct. This change adds the
"host-arch-is-64bit" feature to allow tests to restrict themselves to
the 64-bit case.
Irreducible loop metadata for more accurate block frequency under PGO.
Summary:
Currently the block frequency analysis is an approximation for irreducible
loops.
The new irreducible loop metadata is used to annotate the irreducible loop
headers with their header weights based on the PGO profile (currently this is
approximated to be evenly weighted) and to help improve the accuracy of the
block frequency analysis for irreducible loops.
Shoaib Meenai [Thu, 2 Nov 2017 21:43:32 +0000 (21:43 +0000)]
[tools] Add option to install binutils symlinks
The LLVM tools can be used as a replacement for binutils, in which case
it's convenient to create symlinks with the binutils names. Add support
for these symlinks in the build system. As with any other llvm tool
symlinks, the user can limit the installed symlinks by only adding the
desired ones to `LLVM_TOOLCHAIN_TOOLS`.
Anna Thomas [Thu, 2 Nov 2017 21:21:02 +0000 (21:21 +0000)]
[LoopPredication] Enable predication when latchCheckIV is wider than rangeCheck
Summary:
This patch allows us to predicate range checks that have a type narrower than
the latch check type. We leverage SCEV analysis to identify a truncate for the
latchLimit and latchStart.
There is also safety checks in place which requires the start and limit to be
known at compile time. We require this to make sure that the SCEV truncate expr
for the IV corresponding to the latch does not cause us to lose information
about the IV range.
Added tests show the loop predication over range checks that are of various
types and are narrower than the latch type.
This enhancement has been in our downstream tree for a while.
Shoaib Meenai [Thu, 2 Nov 2017 20:33:36 +0000 (20:33 +0000)]
[cmake] Remove policy conditionals
LLVM now requires a minimum of cmake 3.4.3, and all the policies
currently being set are present in that cmake version, so the
conditionals will always be true and are therefore unnecessary. The
movation is that the conditionals can give the false impression that the
policy settings are optional, whereas for example it's necessary to set
CMP0056 in order for `check_linker_flags` to operate correctly after
r316972. Inline the project version and language setting in the process.
Martin Storsjo [Thu, 2 Nov 2017 20:05:20 +0000 (20:05 +0000)]
[test] Move llvm-lib tests into tools/llvm-lib. NFC.
Similarly to SVN r317189 for llvm-dlltool, these are probably
easier to find in a tools subdirectory with a name identical to
the tool, than in a toplevel directory with a different name.
This matches the move of LibDriver itself in SVN r302995.
Craig Topper [Thu, 2 Nov 2017 19:13:34 +0000 (19:13 +0000)]
[X86] Simplify the pentium4 code in getHostCPUName to be based on feature flags. Don't use 'x86-64' ever.
'x86-64' has started to reflect a sort of generic tuning flag for more modern 64-bit CPUs. We probably shouldn't be using it as the name of an unidentifiable pentium4. So use nocona for all 64-bit pentium4s instead.
Craig Topper [Thu, 2 Nov 2017 19:13:32 +0000 (19:13 +0000)]
[X86] Change getHostCPUName fallback code to not select 'x86-64' for unknown CPUs in family 6 that has 64-bit support but not any newer SSE features. Use 'core2' instead
We know that's the earliest CPU with 64-bit support. x86-64 has taken on a role of representing a more modern 64-bit CPU so we probably shouldn't be using that when we can't identify things.
Anna Thomas [Thu, 2 Nov 2017 18:24:04 +0000 (18:24 +0000)]
Strip off invariant.start because memory locations arent invariant
The original change was reverted in rL317217 because of the failure in
the RS4GC testcase. I couldn't reproduce the failure on my local machine
(macbook) but could reproduce it on a linux box.
The failure was around removing the uses of invariant.start. The fix
here is to just RAUW undef (which was the first implementation in D39388).
This is perfectly valid IR as discussed in the review.
Anna Thomas [Thu, 2 Nov 2017 16:23:31 +0000 (16:23 +0000)]
[RS4GC] Strip off invariant.start because memory locations arent invariant
Summary:
Invariant.start on memory locations has the property that the memory
location is unchanging. However, this is not true in the face of
rewriting statepoints for GC.
Teach RS4GC about removing invariant.start so that optimizations after
RS4GC does not incorrect sink a load from the memory location past a
statepoint.
Clement Courbet [Thu, 2 Nov 2017 15:02:51 +0000 (15:02 +0000)]
[ExpandMemCmp] Split ExpandMemCmp from CodeGen into its own pass.
Summary:
This is mostly a noop (most of the test diffs are renamed blocks).
There are a few temporary register renames (eax<->ecx) and a few blocks are
shuffled around.
Ayman Musa [Thu, 2 Nov 2017 13:07:06 +0000 (13:07 +0000)]
[X86] Fix bug in legalize vector types - Split large loads
When splitting a large load to smaller legally-typed loads, the last load should be padded to reach the size of the previous one so a CONCAT_VECTORS node could reunite them again.
The code currently pads the last load to reach the size of the first load (instead of the previous).
Simon Dardis [Thu, 2 Nov 2017 12:47:22 +0000 (12:47 +0000)]
[mips] Use register scavenging with MSA.
MSA stores and loads to the stack are more likely to require an
emergency GPR spill slot due to the smaller offsets available
with those instructions.
Handle this by overestimating the size of the stack by determining
the largest offset presuming that all callee save registers are
spilled and accounting of incoming arguments when determining
whether an emergency spill slot is required.
Summary:
SpeculativelyExecuteBB can flatten the CFG by doing
speculative execution followed by a select instruction.
When the speculatively executed BB contained dbg intrinsics
the result could be a little bit weird, since those dbg
intrinsics were inserted before the select in the flattened
CFG. So when single stepping in the debugger, printing the
value of the variable referenced in the dbg intrinsic, it
could happen that it looked like the variable had values
that never actually were assigned to the variable.
This patch simply discards all dbg intrinsics that were found
in the speculatively executed BB.
This can create constants which are too large to use as an immediate.
Many ALU operations are also able of performing the shl, so we can
unfold the transformation to prevent a mov imm instruction from being
generated.
Other patterns, such as b + ((a << 1) | 510), can also be simplified
in the same manner.
The patch updates sched numbers for YMM AVX instrs such as VMOVx, VORx, VXOR, VPERMILx, VBROADCASTx, etc.
PR32857 should be closed.
Differential Revision: https://reviews.llvm.org/D39227
Craig Topper [Thu, 2 Nov 2017 03:32:49 +0000 (03:32 +0000)]
[X86] Simplify the detection of pentium-mmx in Host.cpp.
Rather than looking at model numbers just check for the mmx feature flag. While there promote INTEL_PENTIUM_MMX to a CPU type instead of a subtype so that we don't have weird type with only one subtype.
Shoaib Meenai [Thu, 2 Nov 2017 01:07:37 +0000 (01:07 +0000)]
[cmake] Switch FATAL_ERROR to SEND_ERROR
It's possible for multiple distribution components to have missing
targets, and it's a lot more convenient to get all those errors in one
shot rather than having to fix them individually.
Jake Ehrlich [Wed, 1 Nov 2017 23:14:48 +0000 (23:14 +0000)]
[yaml2obj][ELF] Add support for setting alignment in program headers
Sometimes program headers have larger alignments than any of the
sections they contain. Currently yaml2obj can't produce such files. A
bug recently appeared in llvm-objcopy that failed in such a case. I'd
like to be able to add tests to llvm-objcopy for such cases.
This change adds an optional alignment parameter to program headers that
will be used instead of calculating the alignment.
whitequark [Wed, 1 Nov 2017 22:18:52 +0000 (22:18 +0000)]
[LLVM-C] Expose functions to create debug locations via DIBuilder.
These include:
* Several functions for creating an LLVMDIBuilder,
* LLVMDIBuilderCreateCompileUnit,
* LLVMDIBuilderCreateFile,
* LLVMDIBuilderCreateDebugLocation.
Simon Pilgrim [Wed, 1 Nov 2017 21:52:29 +0000 (21:52 +0000)]
[X86][SSE] Add PACKUS support to LowerTruncate
Similar to the existing code to lower to PACKSS, we can use PACKUS if the input vector's leading zero bits extend all the way to the packed/truncated value.
We have to account for pre-SSE41 targets not supporting PACKUSDW
Rui Ueyama [Wed, 1 Nov 2017 21:38:14 +0000 (21:38 +0000)]
Rewrite FileOutputBuffer as two separate classes.
This patch is to rewrite FileOutputBuffer as two separate classes;
one for file-backed output buffer and the other for memory-backed
output buffer. I think the new code is easier to follow because two
different implementations are now actually separated as different
classes.
Unlike the previous implementation, the class that does not replace the
final output file using rename(2) does not create a temporary file at
all. Instead, it allocates memory using mmap(2) and use it. I think
this is an improvement because it is now guaranteed that the temporary
memory region doesn't trigger any I/O and there's now zero chance to
leave a temporary file behind. Also, it shouldn't impose new restrictions
because were using mmap IO too.
Craig Topper [Wed, 1 Nov 2017 21:00:59 +0000 (21:00 +0000)]
[X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit VPALIGND/Q into VPALIGNR if the extended registers aren't being used.
This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding.
Dehao Chen [Wed, 1 Nov 2017 20:26:47 +0000 (20:26 +0000)]
Include GUIDs from the same module when computing GUIDs that needs to be imported.
Summary: In the compile phase of SamplePGO+ThinLTO, ICP is not invoked. Instead, indirect call targets will be included as function metadata for ThinIndex to buidl the call graph. This should not only include functions defined in other modules, but also functions defined in the same module, otherwise ThinIndex may find the callee dead and eliminate it, while ICP in backend will revive the symbol, which leads to undefined symbol.
Daniel Sanders [Wed, 1 Nov 2017 19:57:57 +0000 (19:57 +0000)]
[globalisel][tablegen] Add support for multi-insn emission
The importer will now accept nested instructions in the result pattern such as
(ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction
def's a single vreg and the parent instruction consumes a single vreg where a
nested instruction is specified. The importer will automatically create a vreg
to connect the two using the type information from the pattern. This vreg will
be constrained to the register classes given in the instruction definitions*.
* REG_SEQUENCE is explicitly rejected because of this. The definition doesn't
constrain to a register class and it therefore needs special handling.
Craig Topper [Wed, 1 Nov 2017 18:10:06 +0000 (18:10 +0000)]
[X86] Prevent fast isel from folding loads into the instructions listed in hasPartialRegUpdate.
This patch moves the check for opt size and hasPartialRegUpdate into the lower level implementation of foldMemoryOperandImpl to catch the entry point that fast isel uses.
We're still folding undef register instructions in AVX that we should also probably disable, but that's a problem for another patch.
Unfortunately, this requires reordering a bunch of functions which is why the diff is so large. I can do the function reordering separately if we want.
LTO: Apply global DCE to ThinLTO modules at LTO opt level 0.
This is necessary because DCE is applied to full LTO modules. Without
this change, a reference from a dead ThinLTO global to a dead full
LTO global will result in an undefined reference at link time.
This problem is only observable when --gc-sections is disabled, or
when targeting COFF, as the COFF port of lld requires all symbols to
have a definition even if all references are dead (this is consistent
with link.exe).
This change also adds an EliminateAvailableExternally pass at -O0. This
is necessary to handle the situation on Windows where a non-prevailing
copy of a linkonce_odr function has an SEH filter function; any
such filters must be DCE'd because they will contain a call to the
llvm.localrecover intrinsic, passing as an argument the address of the
function that the filter belongs to, and llvm.localrecover requires
this function to be defined locally.
Petar Jovanovic [Wed, 1 Nov 2017 16:04:11 +0000 (16:04 +0000)]
Correct dwarf unwind information in function epilogue for X86
This patch aims to provide correct dwarf unwind information in function
epilogue for X86.
It consists of two parts. The first part inserts CFI instructions that set
appropriate cfa offset and cfa register in emitEpilogue() in
X86FrameLowering. This part is X86 specific.
The second part is platform independent and ensures that:
- CFI instructions do not affect code generation
- Unwind information remains correct when a function is modified by
different passes. This is done in a late pass by analyzing information
about cfa offset and cfa register in BBs and inserting additional CFI
directives where necessary.
Changed CFI instructions so that they:
- are duplicable
- are not counted as instructions when tail duplicating or tail merging
- can be compared as equal
Added CFIInstrInserter pass:
- analyzes each basic block to determine cfa offset and register valid at
its entry and exit
- verifies that outgoing cfa offset and register of predecessor blocks match
incoming values of their successors
- inserts additional CFI directives at basic block beginning to correct the
rule for calculating CFA
Having CFI instructions in function epilogue can cause incorrect CFA
calculation rule for some basic blocks. This can happen if, due to basic
block reordering, or the existence of multiple epilogue blocks, some of the
blocks have wrong cfa offset and register values set by the epilogue block
above them.
CFIInstrInserter is currently run only on X86, but can be used by any target
that implements support for adding CFI instructions in epilogue.
Geoff Berry [Wed, 1 Nov 2017 15:16:50 +0000 (15:16 +0000)]
[BranchProbabilityInfo] Handle irreducible loops.
Summary:
Compute the strongly connected components of the CFG and fall back to
use these for blocks that are in loops that are not detected by
LoopInfo when computing loop back-edge and exit branch probabilities.
Max Kazantsev [Wed, 1 Nov 2017 13:21:56 +0000 (13:21 +0000)]
Revert rL311205 "[IRCE] Fix buggy behavior in Clamp"
This patch reverts rL311205 that was initially a wrong fix. The real problem
was in intersection of signed and unsigned ranges (see rL316552), and the
patch being reverted masked the problem instead of fixing it.
By now, the test against which rL311205 was made works OK even without this
code. This revert patch also contains a test case that demonstrates incorrect
behavior caused by rL311205: it is caused by incorrect choise of signed max
instead of unsigned.
Simon Pilgrim [Wed, 1 Nov 2017 11:47:44 +0000 (11:47 +0000)]
[X86][SSE] Truncate with PACKSS any input with sufficient sign-bits
So far we've only been using PACKSS truncations with 'all-bits or zero-bits' patterns (vector comparison results etc.). When really we can safely use it for any case as long as the number of sign bits reach down to the last 16-bits (or 8-bits if we're truncating to bytes).
The next steps after this is add the equivalent support for PACKUS and to support packing to sub-128 bit vectors for truncating stores etc.
Florian Hahn [Wed, 1 Nov 2017 09:48:12 +0000 (09:48 +0000)]
[CodeExtractor] Fix iterator invalidation in findOrCreateBlockForHoisting.
Summary:
By replacing branches to CommonExitBlock, we remove the node from
CommonExitBlock's predecessors, invalidating the iterator. The problem
is exposed when the common exit block has multiple predecessors and
needs to sink lifetime info. The modification in the test case trigger
the issue.
projects / llvm / log