NAKAMURA Takumi [Thu, 17 Feb 2011 05:56:41 +0000 (05:56 +0000)]
lit/TestingConfig.py: Add the environment variable PRINTF_EXPONENT_DIGITS as workaround [PR6745] for mingw's tests. Danil Malyshev suggested this.
FIXME: It does not improve MSVC's issue.
[Danil Malyshev] Defining PRINTF_EXPONENT_DIGITS env is the suggested way to make MinGW ANSI/POSIX compatible. This is not only about the case we are discussing, but in general, I'd like to have explicitly defined compatibility mode for all the tests running on MinGW.
Eric Christopher [Wed, 16 Feb 2011 01:10:03 +0000 (01:10 +0000)]
The change for PR9190 wasn't quite right. We need to avoid making the
transformation if we can't legally create a build vector of the correct
type. Check that we can make the transformation first, and add a TODO to
refactor this code with similar cases.
Fixes: PR9223 and rdar://9000350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125631 91177308-0d34-0410-b5e6-96231b3b80d8
Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as well.
This is necessary to avoid a crash in certain tangled situations where a kill
flag is first correctly moved to a merged instruction, and then needs to be
moved again:
STR %R0, a...
STR %R0<kill>, b...
First becomes:
STR %R0, b...
STM a, %R0<kill>, ...
and then:
STM a, %R0, ...
STM b, %R0<kill>, ...
We can now remove the kill flag from the merged STM when needed. 8960050.
Devang Patel [Tue, 15 Feb 2011 17:56:09 +0000 (17:56 +0000)]
Ignore DBG_VALUE machine instructions while constructing instruction ranges based on location info.
Machine instruction range consisting of only DBG_VALUE MIs only contributes consecutive labels in assembly output, which is harmless, and empty scope entry in DebugInfo, which confuses debugger tools.
Move more fragments of spill weight calculation into CalcSpillWeights.h
Simplify the spill weight calculation a bit by bypassing
getApproximateInstructionCount() and using LiveInterval::getSize() directly.
This changes the computed spill weights, but only by a constant factor in each
function. It should not affect how spill weights compare against each other, and
so it shouldn't affect code generation.
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
Chris Lattner [Mon, 14 Feb 2011 07:35:09 +0000 (07:35 +0000)]
add a new ArrayRef class. This is intended to replace the idiom we
use in many places where we pass a pointer and size to abstract APIs
that can take C arrays, std::vector, SmallVector, etc. It is to arrays
what StringRef is to strings.
Chris Lattner [Sun, 13 Feb 2011 22:25:43 +0000 (22:25 +0000)]
Enhance ComputeMaskedBits to know that aligned frameindexes
have their low bits set to zero. This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.
Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively. Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST). The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.
Chris Lattner [Sun, 13 Feb 2011 19:09:16 +0000 (19:09 +0000)]
Revisit my fix for PR9028: the issue is that DAGCombine was
generating i8 shift amounts for things like i1024 types. Add
an assert in getNode to prevent this from occuring in the future,
fix the buggy transformation, revert my previous patch, and
document this gotcha in ISDOpcodes.h
Duncan Sands [Sun, 13 Feb 2011 17:15:40 +0000 (17:15 +0000)]
Teach instsimplify that X+Y>=X+Z is the same as Y>=Z if neither side overflows,
plus some variations of this. According to my auto-simplifier this occurs a lot
but usually in combination with max/min idioms. Because max/min aren't handled
yet this unfortunately doesn't have much effect in the testsuite.
Nadav Rotem [Sun, 13 Feb 2011 15:45:34 +0000 (15:45 +0000)]
Fix a regression from r125393;
It caused a crash in MultiSource/Benchmarks/Bullet.
Opt hit an assertion with "opt -std-compile-opts" because
Constant::getAllOnesValue doesn't know how to handle floats.
This patch added a test to reproduce the problem and a check that the
destination vector is of integer type.
Chris Lattner [Sun, 13 Feb 2011 09:10:56 +0000 (09:10 +0000)]
when legalizing extremely wide shifts, make sure that
the shift amounts are in a suitably wide type so that
we don't generate out of range constant shift amounts.
Chris Lattner [Sun, 13 Feb 2011 09:02:52 +0000 (09:02 +0000)]
fix visitShift to properly zero extend the shift amount if the provided operand
is narrower than the shift register. Doing an anyext provides undefined bits in
the top part of the register.
Chris Lattner [Sun, 13 Feb 2011 03:14:49 +0000 (03:14 +0000)]
teach SCEV that the scale and addition of an inbounds gep don't NSW.
This fixes a FIXME in scev-aa.ll (allowing a new no-alias result) and
generally makes things more precise.
Reid Kleckner [Sat, 12 Feb 2011 23:24:13 +0000 (23:24 +0000)]
Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.
These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.
Nadav Rotem [Sat, 12 Feb 2011 14:40:33 +0000 (14:40 +0000)]
A fix for 9165.
The DAGCombiner created illegal BUILD_VECTOR operations.
The patch added a check that either illegal operations are
allowed or that the created operation is legal.
Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.
Chris Lattner [Fri, 11 Feb 2011 21:43:33 +0000 (21:43 +0000)]
Per discussion with Dan G, inbounds geps *certainly* can have
unsigned overflow (e.g. "gep P, -1"), and while they can have
signed wrap in theoretical situations, modelling an AddRec as
not having signed wrap is going enough for any case we can
think of today. In the future if this isn't enough, we can
revisit this. Modeling them as having NUW isn't causing any
known problems either FWIW.
Chris Lattner [Fri, 11 Feb 2011 21:37:43 +0000 (21:37 +0000)]
When lowering an inbounds gep, the intermediate adds can have
unsigned overflow (e.g. due to a negative array index), but
the scales on array size multiplications are known to not
sign wrap.
Nate Begeman [Fri, 11 Feb 2011 20:53:29 +0000 (20:53 +0000)]
Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.
This avoids moving each element to the integer register file and calling __divsi3 etc. on it.
Nadav Rotem [Fri, 11 Feb 2011 19:20:37 +0000 (19:20 +0000)]
Fix #9190
The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.
Douglas Gregor [Fri, 11 Feb 2011 18:13:20 +0000 (18:13 +0000)]
Poison the relational operators ==, !=, <, <=, >=, > on llvm::Optional
objects, since they'll end up using the implicit conversion to "bool"
and causing some very "fun" surprises.
Cameron Zwarich [Fri, 11 Feb 2011 06:08:28 +0000 (06:08 +0000)]
Make LoopUnswitch preserve ScalarEvolution by just forgetting everything about
a loop when unswitching it. It only does this in the complex case, because
everything should be fine already in the simple case.
projects / llvm / log