lld, llvm-dlltool, llvm-lib: Use getAsString() instead of getSpelling() for printing unknown args
Since OPT_UNKNOWN args never have any values and consist only of
spelling (and are never aliased), this doesn't make any difference in
practice, but it's more consistent with Arg's guidance to use
getAsString() for diagnostics, and it matches what clang does.
Also tweak two tests to use an unknown option that contains '=' for
additional coverage while here. (The new tests pass fine with the old
code too though.)
Robert Lougher [Fri, 5 Jul 2019 12:20:21 +0000 (12:20 +0000)]
This reverts r365061 and r365062 (test update)
Revision r365061 changed a skip of debug instructions for a skip
of meta instructions. This is not safe, as IMPLICIT_DEF is classed
as a meta instruction.
[FileCheck] Fix comment in parseNumericVariableUse
Summary:
Comment explaining the interaction between parsing of numeric variable
definition and uses in parseNumericVariableUse is stale since it
suggests both use and definition parsing is done in the same function.
This was the case in a previous version of the patch committed as 71d3f227a790d6cf39d8c6267940e0dc0c237e11 but is no longer the case. This
patch updates the comment accordingly.
Summary:
Both callers of parseNumericVariableDefinition() perform the same extra
check that no character is found after the variable name. This patch
factors out this check into parseNumericVariableDefinition().
[ThinLTO] Attempt to recommit r365040 after caching fix
It's possible that some function can load and store the same
variable using the same constant expression:
store %Derived* @foo, %Derived** bitcast (%Base** @bar to %Derived**)
%42 = load %Derived*, %Derived** bitcast (%Base** @bar to %Derived**)
The bitcast expression was mistakenly cached while processing loads,
and never examined later when processing store. This caused @bar to
be mistakenly treated as read-only variable. See load-store-caching.ll.
Make joined instances of JoinedOrSeparate flags point to the unaliased args, like all other arg types do
This fixes an 8-year-old regression. r105763 made it so that aliases
always refer to the unaliased option – but it missed the "joined" branch
of JoinedOrSeparate flags. (r162231 then made the Args classes
non-virtual, and r169344 moved them from clang to llvm.)
Back then, there was no JoinedOrSeparate flag that was an alias, so it
wasn't observable. Now /U in CLCompatOptions is a JoinedOrSeparate alias
in clang, and warn_slash_u_filename incorrectly used the aliased arg id
(using the unaliased one isn't really a regression since that warning
checks if the undefined macro contains slash or backslash and only then
emits the warning – and no valid use will pass "-Ufoo/bar" or similar).
Also, lld has many JoinedOrSeparate aliases, and due to this bug it had
to explicitly call `getUnaliasedOption()` in a bunch of places, even
though that shouldn't be necessary by design. After this fix in Option,
these calls really don't have an effect any more, so remove them.
No intended behavior change.
(I accidentally fixed this bug while working on PR29106 but then
wondered why the warn_slash_u_filename broke. When I figured it out, I
thought it would make sense to land this in a separate commit.)
George Rimar [Fri, 5 Jul 2019 11:28:49 +0000 (11:28 +0000)]
[Object/ELF.h] - Improve error reporting.
The errors coming from ELF.h are usually not very
useful because they are uninformative. This patch is a
first step to improve the situation.
I tested this patch with a run of check-llvm and found
that few messages are untested. In this patch, I did not
add more tests but marked all such cases with a "TODO" comment.
For all tested messages I extended the error text to
provide more details (see test cases changed).
- The code tried to pass false to split()'s KeepEmpty parameter, but
instead passed it to MaxSplit. As a result, it would never split on
commas. This has been broken since the flag was added in r278056.
- The code used getSpelling() for getting the argument's values, but
getSpelling() always returns the `/debugtype:` prefix without any
values. So if any /debugtype: flag was passed, it always resulted in
an "unknown option:" warning. (The warning code then used the correct
getValue() for printing the invalid option, so the warning looked
kind of like it made sense.) This regressed in r342894.
Slightly improve the test coverage of this feature (but since I don't
know what this flag actually does, there's still no test for the correct
semantics), and add a comment to getSpelling() explaining what it does.
David Green [Fri, 5 Jul 2019 10:02:43 +0000 (10:02 +0000)]
[ARM] MVE VMOV immediate handling
This adds some handling for VMOVimm, using the same method that NEON uses. We
create VMOVIMM/VMVNIMM/VMOVFPIMM nodes based on the immediate, and select them
using the now renamed ARMvmovImm/etc. There is also an extra 64bit immediate
mode that I have not yet added here.
Summary:
Use an enum instead of string to hold the output file format in Config.InputFormat and Config.OutputFormat. It's essential to support other output file formats other than ELF.
This patch originally has been submitted as D63239. However, there was an use-of-uninitialized-value bug and reverted in r364379 (git commit 4ee933c).
This patch includes the fix for the bug by setting Config.InputFormat/Config.OutputFormat in parseStripOptions.
[X86] Add custom isel to select ADD/SUB/OR/XOR/AND to their non-immediate forms under optsize when the immediate has additional users.
Summary:
We attempt to prevent folding immediates with multiple users under optsize. But we only do this from store nodes and X86ISD::ADD/SUB/XOR/OR/AND patterns. We don't do it for ISD::ADD/SUB/XOR/OR/AND even though we count them as users when deciding whether to fold into other nodes. This leads to situations where we block folding to a compare for example, but still fold into an AND or OR as seen in PR27202.
Unfortunately touching the isel patterns in tablegen for the ISD::ADD/SUB/XOR/OR/AND opcodes will cause the patterns to be unusable for fast isel. And we don't have a way to make a fast isel only pattern.
To workaround this, this patch adds custom isel in front of the isel table that will select the non-immediate forms if the immediate has additional users. This may create some issues for ANDN and NOT matching. And there's room for improvement with unsigned 32 immediates on 64-bit AND.
This patch needs more thorough test cases, but I wanted to get feedback on the direction. Please send me any other test cases you've seen in the wild.
I think we probably have the same issue with the immediate matching when we fold RMW from X86ISD::ADD/SUB/XOR/OR/AND. And our TEST immedaite shrinking logic. Our cost modeling for immediates that can fit in a sign extended 8-bit immediate on a 16/32/64 bit operation is completely wrong.
I also wonder if we should update the ConstantHoisting cost model and block folding for "opaque" constants. But of course constants can still be created by DAG combine and lowering optimizations.
Alex Brachet [Thu, 4 Jul 2019 22:45:27 +0000 (22:45 +0000)]
[llvm-objcopy] Change handling of output file permissions
Summary: Address bug [[ https://bugs.llvm.org/show_bug.cgi?id=42082 | 42082 ]] where files were always outputted with 0775 permissions. Now, the output file is given either 0666 or 0777 if the object is executable.
[NFC] Make some ObjectFormatType switches covering
Summary:
This patch removes the `default` case from some switches on
`llvm::Triple::ObjectFormatType`, and cases for the missing enumerators
are then added.
For `UnknownObjectFormat`, the action (`llvm_unreachable`) for the
`default` case is kept.
For the other unhandled cases, `report_fatal_error` is used instead.
[DAGCombiner] Don't combine (addcarry (uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry) if the Carry comes from the uaddo.
Summary:
The uaddo won't be removed and the addcarry will still be
dependent on the uaddo. So we'll just increase the use count
of X and Y and potentially require a COPY.
Summary:
Since the changes to introduce vec3 and vec5, INSERT_VECTOR for these
sizes has been marked "expand", which made LegalizeDAG lower it to loads
and stores via a stack slot. The code got optimized a bit later, but the
now-unused stack slot was never deleted.
This commit avoids that problem by custom lowering INSERT_SUBVECTOR into
an EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT for each element in the
subvector to insert.
[InstCombine] allow undef elements when forming splat from chain of insertelements
We allow forming a splat (broadcast) shuffle, but we were conservatively limiting
that to cases where all elements of the vector are specified. It should be safe
from a codegen perspective to allow undefined lanes of the vector because the
expansion of a splat shuffle would become the chain of inserts again.
Forming splat shuffles can reduce IR and help enable further IR transforms.
Motivating bugs:
https://bugs.llvm.org/show_bug.cgi?id=42174
https://bugs.llvm.org/show_bug.cgi?id=16739
Summary:
As explained in D63668, malloc(0) could return a null pointer. llvm-c-test does not handle this case correctly. Instead of calling malloc(0), avoid the operation altogether.
Bitcast v4i32 to v8f32 and back again - it might be worth adding isel patterns for X86PShufd v8i32 on AVX1 targets like we did for X86Blendi to avoid the bitcasts?
Mikael Holmen [Thu, 4 Jul 2019 09:29:18 +0000 (09:29 +0000)]
[Remarks] Silence gcc warning by catching unhandled values in switches
Without this fix gcc (7.4) complains with
../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef)':
../lib/Remarks/RemarkParser.cpp:29:1: error: control reaches end of non-void function [-Werror=return-type]
}
^
../lib/Remarks/RemarkParser.cpp: In function 'std::unique_ptr<llvm::remarks::ParserImpl> formatToParserImpl(llvm::remarks::ParserFormat, llvm::StringRef, const llvm::remarks::ParsedStringTable&)':
../lib/Remarks/RemarkParser.cpp:38:1: error: control reaches end of non-void function [-Werror=return-type]
}
^
The Format enum currently only contains the value YAML which is indeed
already handled in the switches, but gcc complains anyway.
Adding a default case with an llvm_unreachable silences gcc.
David Green [Thu, 4 Jul 2019 08:58:58 +0000 (08:58 +0000)]
[ARM] Favour PL/MI over GE/LT when possible
The arm condition codes for GE is N==V (and for LT is N!=V). If the source of
flags cannot set V (overflow), such as a cmp against #0, then we can use the
simpler PL and MI conditions that only check N. As these PL/MI conditions are
simpler than GE/LT, other passes like the peephole optimiser can have a better
time optimising away the redundant CMPs.
The exception is the VSEL instruction, which cannot take the PL code, so there
the transform favours GE.
James Henderson [Thu, 4 Jul 2019 08:49:04 +0000 (08:49 +0000)]
[docs][llvm-dwarfdump] Remove unnecessary reference to --show-children
The --show-children option description describes what it does, and
references the =<offset> parameter of section dump switches. I don't
think it needs to be explained again in the documentation of the
section dump switches too.
Simon Tatham [Thu, 4 Jul 2019 08:43:20 +0000 (08:43 +0000)]
[TableGen] Allow DAG isel patterns to override default operands.
When a Tablegen instruction description uses `OperandWithDefaultOps`,
isel patterns for that instruction don't have to fill in the default
value for the operand in question. But the flip side is that they
actually //can't// override the defaults even if they want to.
This will be very inconvenient for the Arm backend, when we start
wanting to write isel patterns that generate the many MVE predicated
vector instructions, in the form with predication actually enabled. So
this small Tablegen fix makes it possible to write an isel pattern
either with or without values for a defaulted operand, and have the
default values filled in only if they are not overridden.
If all the defaulted operands come at the end of the instruction's
operand list, there's a natural way to match them up to the arguments
supplied in the pattern: consume pattern arguments until you run out,
then fill in any missing instruction operands with their default
values. But if defaulted and non-defaulted operands are interleaved,
it's less clear what to do. This does happen in existing targets (the
first example I came across was KILLGT, in the AMDGPU/R600 backend),
and of course they expect the previous behaviour (that the default for
those operands is used and a pattern argument is not consumed), so for
backwards compatibility I've stuck with that.
David Green [Thu, 4 Jul 2019 08:41:23 +0000 (08:41 +0000)]
[ARM] MVE bitwise instruction patterns
This adds patterns for the simpler VAND, VORR and VEOR bitwise vector
instructions. It also adjusts the top16Zero PatLeaf to not match on vector
instructions, which can otherwise cause problems.
Fangrui Song [Thu, 4 Jul 2019 04:44:42 +0000 (04:44 +0000)]
[PowerPC] Support constraint code "ww"
Summary:
"ww" and "ws" are both constraint codes for VSX vector registers that
hold scalar double data. "ww" is preferred for float while "ws" is
preferred for double.
Alex Brachet [Thu, 4 Jul 2019 04:41:06 +0000 (04:41 +0000)]
[docs] [NFC] Removed excess spacing
Summary: Removed excess new lines from documentations. As far as I can tell, it seems as though restructured text is agnostic to new lines, the use of new lines was inconsistent and had no effect on how the files were being displayed.
Added array of valid architectures and function returning array.
Modified llvm-lipo to include list of valid architectures in error message for invalid arch.
Lang Hames [Thu, 4 Jul 2019 00:05:12 +0000 (00:05 +0000)]
[JITLink][ORC] Add EHFrameRegistrar interface, use in EHFrameRegistrationPlugin.
Replaces direct calls to eh-frame registration with calls to methods on an
EHFrameRegistrar instance. This allows clients to substitute a registrar that
registers frames in a remote process via IPC/RPC.
Matt Arsenault [Wed, 3 Jul 2019 23:32:29 +0000 (23:32 +0000)]
AMDGPU: Add pass to lower SGPR spills
This is split out from my patches to split register allocation into a
separate SGPR and VGPR phase, and has some parts that aren't yet used
(like maintaining LiveIntervals).
This simplifies making the frame pointer register callee saved. As it
is now, the code to determine callee saves needs to predict all the
possible SGPR spills and how many callee saved VGPRs are needed. By
handling this before PrologEpilogInserter, it's possible to just check
the spill objects that already exist.
Eli Friedman [Wed, 3 Jul 2019 23:12:39 +0000 (23:12 +0000)]
[JumpThreading] Fix threading with unusual PHI nodes.
If the block being cloned contains a PHI node, in general, we need to
clone that PHI node, even though it's trivial. If the operand of the PHI
is an instruction in the block being cloned, the correct value for the
operand doesn't exist until SSAUpdater constructs it.
We usually don't hit this issue because we try to avoid threading across
loop headers, but it's possible to hit this in some cases involving
irreducible CFGs. I added a flag to allow threading across loop headers
to make the testcase easier to understand.
Thomas Lively [Wed, 3 Jul 2019 22:04:54 +0000 (22:04 +0000)]
[WebAssembly] Add option to emit passive segments
Summary:
Adds `--passive-segments` and `--active-segments` flags to control
what kind of segments are emitted. For now the default is always
to emit active segments so this is not a breaking change, but in
the future the default will be changed to passive segments when
shared memory is requested and active segments otherwise. When
passive segments are emitted, corresponding memory.init and
data.drop instructions are emitted in a `__wasm_init_memory`
function that is automatically called at the beginning of
`__wasm_call_ctors`.
This reverts commit 250015bacf7f255abcfb646fb8b6b56ce8be7e01.
r365039 was re-commit of D63197 and failed on Mac. Reid XFAIL'd it, but I'd rather jsut revert and have it fixed properly.
[LoopBase] Strengthen isLoopExiting by requiring that BB must be inside the loop.
Currently isLoopExiting returns true for BBs that are not part of the
loop. To avoid hiding subtle bugs, this patch adds an assertion to make
sure the passed BB is inside the loop
Philip Reames [Wed, 3 Jul 2019 20:03:46 +0000 (20:03 +0000)]
[LFTR] Use SCEVExpander for the pointer limit case instead of manual IR gen
As noted in the test change, this is not trivially NFC, but all of the changes in output are cases where the SCEVExpander form is more canonical/optimal than the hand generation.
Philip Reames [Wed, 3 Jul 2019 18:18:36 +0000 (18:18 +0000)]
[LFTR] Hoist extend expressions outside of loops w/o waiting for LICM
The motivation for this is two fold:
1) Make the output (and thus tests) a bit more readable to a human trying to understand the result of the transform
2) Reduce spurious diffs in a potential future change to restructure all of this logic to use SCEVExpander (which hoists by default)
Joel E. Denny [Wed, 3 Jul 2019 17:31:43 +0000 (17:31 +0000)]
[Bitcode] Update CHECK-DAG usage in tests
This patch adjusts tests not to depend on deprecated FileCheck
behavior that permits overlapping matches within a block of
`CHECK-DAG` directives:
1. `thinlto-function-summary-originalnames.ll`: The directive with the
pattern `<COMBINED` is surely intended to match `<COMBINED ` (note the
trailing space), but it instead matches
`<COMBINED_GLOBALVAR_INIT_REFS`, for which there is a separate
directive. With the deprecated behavior, both directives match the
latter text and neither match the former text. I've adjusted the
former directive so it matches only the former text.
2. `thinlto-summary-local-5.0.ll`: Two directives have identical
patterns when they were clearly meant to have different patterns.
3. `upgrade-pointer-address-space.ll`: There are three identical
directives but only two occurrences of the matching text. With the
deprecated behavior, they always match exactly the same text, so the
behavior can't have been useful. I removed one of the directives and
converted the other two from `CHECK-DAG` to `CHECK`.
[CodeGen] Make branch funnels pass the machine verifier
We previously marked all the tests with branch funnels as
`-verify-machineinstrs=0`.
This is an attempt to fix it.
1) `ICALL_BRANCH_FUNNEL` has no defs. Mark it as `let OutOperandList =
(outs)`
2) After that we hit an assert: ``` Assertion failed: (Op.getValueType()
!= MVT::Other && Op.getValueType() != MVT::Glue && "Chain and glue
operands should occur at end of operand list!"), function AddOperand,
file
/Users/francisvm/llvm/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp,
line 461. ```
The chain operand was added at the beginning of the operand list. Move
that to the end.
3) After that we hit another verifier issue in the pseudo expansion
where the registers used in the cmps and jmps are not added to the
livein lists. Add the `EFLAGS` to all the new MBBs that we create.
[DAGCombine] More diamong carry pattern optimization.
Summary:
This diff improve the capability of DAGCOmbine to generate linear carries propagation in presence of a diamond pattern. It is now able to match a large variety of different patterns rather than some hardcoded one.
Arguably, the codegen in test cases is not better, but this is to be expected. The goal of this transformation is more about canonicalisation than actual optimisation.
projects / llvm / log