Alex Lorenz [Fri, 26 Jun 2015 16:46:11 +0000 (16:46 +0000)]
MIR Serialization: Serialize machine basic block operands.
This commit serializes machine basic block operands. The
machine basic block operands use the following syntax:
%bb.<id>[.<name>]
This commit also modifies the YAML representation for the
machine basic blocks - a new, required field 'id' is added
to the MBB YAML mapping.
The id is used to resolve the MBB references to the
actual MBBs. And while the name of the MBB can be
included in a MBB reference, this name isn't used to
resolve MBB references - as it's possible that multiple
MBBs will reference the same BB and thus they will have the
same name. If the name is specified, the parser will verify
that it is equal to the name of the MBB with the specified id.
Aaron Ballman [Fri, 26 Jun 2015 14:51:22 +0000 (14:51 +0000)]
Silencing spurious MSVC C4189 warnings regarding local variables that are initialized but not used; NFC. This bug has been reported to Microsoft (https://connect.microsoft.com/VisualStudio/feedback/details/1475983).
Toma Tabacu [Fri, 26 Jun 2015 13:20:17 +0000 (13:20 +0000)]
[mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.
Rafael Espindola [Fri, 26 Jun 2015 12:18:49 +0000 (12:18 +0000)]
Simplify getSymbolType.
This is still a really odd function. Most calls are in object format specific
contexts and should probably be replaced with a more direct query, but at least
now this is not too obnoxious to use.
Hao Liu [Fri, 26 Jun 2015 02:32:07 +0000 (02:32 +0000)]
[AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses.
E.g. Lower an interleaved load:
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
into:
%ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
%vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
%vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
E.g. Lower an interleaved store:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
into:
%sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
%sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
%sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
Hao Liu [Fri, 26 Jun 2015 02:10:27 +0000 (02:10 +0000)]
[InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.
E.g. An interleaved load (Factor = 2):
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
%v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.
E.g. An interleaved store (Factor = 3):
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.
Alexey Samsonov [Fri, 26 Jun 2015 00:00:47 +0000 (00:00 +0000)]
[ASan] Use llvm::getDISubprogram() to get function entry debug location.
It can be more robust than copying debug info from first non-alloca
instruction in the entry basic block. We use the same strategy in
coverage instrumentation.
AsmPrinter: Use an intrusively linked list for DIE::Children
Replace the `std::vector<>` for `DIE::Children` with an intrusively
linked list. This is a strict memory improvement: it requires no
auxiliary storage, and reduces `sizeof(DIE)` by one pointer. It also
factors out the DIE-related malloc traffic.
This drops llc memory usage from 735 MB down to 718 MB, or ~2.3%.
(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)
Change `DIE::Values` to a singly linked list, where each node is
allocated on a `BumpPtrAllocator`. In order to support `push_back()`,
the list is circular, and points at the tail element instead of the
head. I abstracted the core list logic out to `IntrusiveBackList` so
that it can be reused for `DIE::Children`, which also cares about
`push_back()`.
This drops llc memory usage from 799 MB down to 735 MB, about 8%.
(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)
Anna Zaks [Thu, 25 Jun 2015 23:35:48 +0000 (23:35 +0000)]
[asan] Do not instrument special purpose LLVM sections.
Do not instrument globals that are placed in sections containing "__llvm"
in their name.
This fixes a bug in ASan / PGO interoperability. ASan interferes with LLVM's
PGO, which places its globals into a special section, which is memcpy-ed by
the linker as a whole. When those goals are instrumented, ASan's memcpy wrapper
reports an issue.
Adrian Prantl [Thu, 25 Jun 2015 23:19:19 +0000 (23:19 +0000)]
Debug Info: Add basic test coverage for the DWARF encoding of bitfields.
While looking at a couple of bugs in the debug info output for bitfields
I noticed that there wasn't a single regression test to test my changes
against, so here's a start.
Frederic Riss [Thu, 25 Jun 2015 21:57:33 +0000 (21:57 +0000)]
IAS: Use the root macro instanciation for location
r224810 fixed the handling of macro debug locations in AsmParser. This patch
fixes the logic to actually do what was intended: it uses the first macro of
the macro stack instead of the last one. The updated testcase shows that the
current scheme doesn't work when macro instanciations are nested and multiple
files are used.
Split out code to patch up the `DW_AT_stmt_list` for the cloned DIE, and
reorganize it so that it doesn't depend on `DIE::values_begin()` and
`DIE::values_end()` (which I'm trying to kill off).
David Blaikie and I talked about adding a range-algorithm version of
`std::find_if()`, but the assertion *still* required getting at the end
iterator. IMO, a separate helper function with an early return is
easier to reason about here.
A follow-up commit that removes `DIE::setValue()` and mutates the
`DIEValue` directly is coming shortly.
Jingyue Wu [Thu, 25 Jun 2015 20:14:47 +0000 (20:14 +0000)]
[InstCombine] call SimplifyICmpInst with correct context
Summary:
Fixes PR23809. Without passing the context to SimplifyICmpInst, we would
use the assume to prove that the condition feeding the assume is
trivially true (see isValidAssumeForContext in ValueTracking.cpp),
causing the removal of the assume which may be useful for later
optimizations.
Toma Tabacu [Thu, 25 Jun 2015 12:44:38 +0000 (12:44 +0000)]
[mips] [IAS] Refactor the emitDirectiveModuleFP() functions. NFC.
Summary:
Simplify emitDirectiveModuleFP() by having it just print the current information
from MipsABIFlagsSection and doing an updateABIInfo() before such calls.
This prevents us from forgetting to update the STI.FeatureBits,
because updateABIInfo() uses those to update the MipsABIFlagsSection object,
and also makes sure we use the update mechanism from MipsABIFlagsSection.
Ulrich Weigand [Thu, 25 Jun 2015 11:52:36 +0000 (11:52 +0000)]
[SystemZ] Only attempt RxSBG optimization for integer types
As pointed out by Justin Bogner (see r240520), SystemZDAGToDAGISel::Select
currently attempts to convert boolean operations into RxSBG even on some
non-integer types (in particular, vector types). This would not work in
any case, and it happened to trigger undefined behaviour in allOnes.
This patch verifies that we have a (<= 64-bit) integer type before
attempting to perform this optimization.
Toma Tabacu [Thu, 25 Jun 2015 10:56:57 +0000 (10:56 +0000)]
[mips] [IAS] Refactor the emitDirectiveModuleOddSPReg() functions. NFC.
Summary:
We can simplify emitDirectiveModuleOddSPReg() by having it print the current OddSPReg information
from MipsABIFlagsSection and doing an updateABIInfo() before such calls.
This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object,
and also makes sure we use the update mechanism from MipsABIFlagsSection.
Toma Tabacu [Thu, 25 Jun 2015 09:52:02 +0000 (09:52 +0000)]
[mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.
Summary:
In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser.
This means that we can only parse one level of inner parentheses.
In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions
(except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression().
r240214 fixed some UB in IndVarSimplify, and it needed a temporary
`WeakVH` to do it. Add `simplify_type<const WeakVH>` so that this
temporary isn't necessary.
Douglas Katzman [Wed, 24 Jun 2015 22:04:55 +0000 (22:04 +0000)]
[X86] Simplify some stuff in X86DisassemblerDecoder. NFC
- Deciding that insn->sibIndex is SIB_INDEX_NONE does not require another
check beyond the fully decoded bits being equal to 0x4.
The expression insn->sibIndex == SIB_INDEX_sib could not have been true unless
index were 0x4, because SIB_INDEX_sib is merely the range base (SIB_INDEX_EAX)
plus 4. Respectively SIB_INDEX_sib64.
- Don't use a switch statement to perform left-shift.
Akira Hatanaka [Wed, 24 Jun 2015 20:34:35 +0000 (20:34 +0000)]
[If Converter] Convert recursion to iteration.
This commit makes changes to IfConverter::AnalyzeBlock to use iteration instead
of recursion. Previously, this function would get called recursively a large
number of times and eventually segfault when a function with the following CFG
was compiled:
BB0:
if (condition0)
goto BB1
goto BB2
BB1:
goto BB2
BB2:
if (condition1)
goto BB3
goto BB4
BB3:
...
(repeat until BB7488)
Jingyue Wu [Wed, 24 Jun 2015 20:20:16 +0000 (20:20 +0000)]
Add NVPTXPeephole pass to reduce unnecessary address cast
Summary:
This patch first change the register that holds local address for stack
frame to %SPL. Then the new NVPTXPeephole pass will try to scan the
following pattern
Rafael Espindola [Wed, 24 Jun 2015 19:57:32 +0000 (19:57 +0000)]
Make computeSymbolSizes never fail.
On ELF that was already the case since getting the size of a symbol
never fails.
On MachO and COFF we could fail trying to get the section of a symbol. But
we don't really need the section, just the section number to know if two
symbols are in the same section or not.
Alex Lorenz [Wed, 24 Jun 2015 19:56:10 +0000 (19:56 +0000)]
MIR Serialization: Serialize simple MachineRegisterInfo attributes.
This commit serializes the 3 scalar boolean attributes from the
MachineRegisterInfo class: IsSSA, TracksRegLiveness, and
TracksSubRegLiveness. These attributes are serialized as part
of the machine function YAML mapping.
Jingyue Wu [Wed, 24 Jun 2015 19:28:40 +0000 (19:28 +0000)]
[LSR] canonicalize Prod*(1<<C) to Prod<<C
Summary:
Because LSR happens at a late stage where mul of a power of 2 is
typically canonicalized to shl, this canonicalization emits code that
can be better CSE'ed.
Test Plan:
Transforms/LoopStrengthReduce/shl.ll shows how this change makes GVN more
powerful. Fixes some existing tests due to this change.
The old pattern was to call replaceUsesOfWithOnConstant which was overridden by
subclasses. Those could then call replaceUsesOfWithOnConstantImpl on Constant
to handle deleting the current value.
To be consistent with other parts of the code, this has been changed so that we
call the method on Constant, and that dispatches to an Impl on subclasses.
As part of this, it made sense to rename the methods to be more descriptive. The
new name is Constant::handleOperandChange, and it requires that all subclasses of
Constant implement handleOperandChangeImpl, even if they just throw an error if
they shouldn't be called.
projects / llvm / log