]> granicus.if.org Git - llvm/log
llvm
9 years agoMerging r236457 and r236635:
Tim Northover [Fri, 12 Jun 2015 15:57:35 +0000 (15:57 +0000)]
Merging r236457 and r236635:

------------------------------------------------------------------------
r236457 | tnorthover | 2015-05-04 13:41:51 -0700 (Mon, 04 May 2015) |
9 lines

CodeGen: match up correct insertvalue indices when assessing tail
calls.

When deciding whether a value comes from the aggregate or inserted
value of an insertvalue instruction, we compare the indices against
those of the location we're interested in. One of the lists needs
reversing because the input data is backwards (so that modifications
take place at the end of the SmallVector), but we were reversing both
before leading to incorrect results.

------------------------------------------------------------------------
r236635 | tnorthover | 2015-05-06 13:07:38 -0700 (Wed, 06 May 2015) |
12 lines

CodeGen: move over-zealous assert into actual if statement.

It's quite possible to encounter an insertvalue instruction that's
more deeply nested than the value we're looking for, but when that
happens we really mustn't compare beyond the end of the index array.

Since I couldn't see any guarantees about what comparisons std::equal
makes, we probably need to directly check the size beforehand. In
practice, I suspect most std::equal implementations would probably
bail early, which would be OK.  But just in case...

rdar://20834485

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@239611 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoBump version to 3.6.2
Tom Stellard [Mon, 1 Jun 2015 14:30:22 +0000 (14:30 +0000)]
Bump version to 3.6.2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@238746 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Update release notes to account for revert.
Daniel Sanders [Fri, 15 May 2015 10:06:38 +0000 (10:06 +0000)]
[mips] Update release notes to account for revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237433 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert r235869 - [mips] Avoid redundant sign extension of the result of binary bitwis...
Daniel Sanders [Fri, 15 May 2015 10:05:22 +0000 (10:05 +0000)]
Revert r235869 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

It introduced two regressions (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) on 3 out of 23 cross-compilation
test-runs used by Mips for release validation.

The issue is that on 64-bit targets comparisons such as BEQ compare the whole
GPR64 but incorrectly tell the instruction selector that they operate on
GPR32's. This leads to the elimination of i32->i64 extensions that are actually
required by comparisons to work correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237432 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226124:
Tom Stellard [Mon, 11 May 2015 19:46:44 +0000 (19:46 +0000)]
Merging r226124:

------------------------------------------------------------------------
r226124 | hans | 2015-01-14 23:36:20 -0500 (Wed, 14 Jan 2015) | 2 lines

utils/release/tag.sh: fix -revision vs. -rc check

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@237015 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229413:
Tom Stellard [Fri, 8 May 2015 14:13:47 +0000 (14:13 +0000)]
Merging r229413:

------------------------------------------------------------------------
r229413 | atrick | 2015-02-16 13:10:47 -0500 (Mon, 16 Feb 2015) | 16 lines

AArch64: Safely handle the incoming sret call argument.

This adds a safe interface to the machine independent InputArg struct
for accessing the index of the original (IR-level) argument. When a
non-native return type is lowered, we generate the hidden
machine-level sret argument on-the-fly. Before this fix, we were
representing this argument as OrigArgIndex == 0, which is an outright
lie. In particular this crashed in the AArch64 backend where we
actually try to access the type of the original argument.

Now we use a sentinel value for machine arguments that have no
original argument index. AArch64, ARM, Mips, and PPC now check for this
case before accessing the original argument.

Fixes <rdar://19792160> Null pointer assertion in AArch64TargetLowering

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236856 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r234977:
Tom Stellard [Thu, 7 May 2015 22:09:33 +0000 (22:09 +0000)]
Merging r234977:

------------------------------------------------------------------------
r234977 | lhames | 2015-04-15 00:46:01 -0400 (Wed, 15 Apr 2015) | 5 lines

[RuntimeDyld] Add casts to make delta computation 64-bit.

Hopefully this will fix the i686/msvc build failure described at:
http://bb.pgr.jp/builders/ninja-clang-i686-msc18-R/builds/803

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236784 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230564:
Tom Stellard [Tue, 5 May 2015 14:43:00 +0000 (14:43 +0000)]
Merging r230564:

------------------------------------------------------------------------
r230564 | spatel | 2015-02-25 17:46:08 -0500 (Wed, 25 Feb 2015) | 8 lines

only propagate equality comparisons of FP values that we are certain are non-zero

This is a follow-on to r227491 which tightens the check for propagating FP
values. If a non-constant value happens to be a zero, we would hit the same
bug as before.

Bug noted and patch suggested by Eli Friedman.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236499 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r236307:
Tom Stellard [Mon, 4 May 2015 19:50:17 +0000 (19:50 +0000)]
Merging r236307:

------------------------------------------------------------------------
r236307 | thomas.stellard | 2015-04-30 23:44:09 -0400 (Thu, 30 Apr 2015) | 4 lines

R600/SI: Add VCC as an implict def of SI_KILL

When SI_KILL has a register operand, its lowered form writes to vcc.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236452 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r236306:
Tom Stellard [Mon, 4 May 2015 19:50:16 +0000 (19:50 +0000)]
Merging r236306:

------------------------------------------------------------------------
r236306 | thomas.stellard | 2015-04-30 23:44:08 -0400 (Thu, 30 Apr 2015) | 11 lines

R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass

This pass was generating 'Instruction does not dominate all uses!'
errors for programs which had loops with a condition variable that
depended on the result of a phi instruction from outside of the loop.

The pass was inserting new phi nodes outside of the loop which used values
defined inside the loop.

http://bugs.freedesktop.org/show_bug.cgi?id=90056

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236451 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r235662:
Tom Stellard [Mon, 4 May 2015 19:50:14 +0000 (19:50 +0000)]
Merging r235662:

------------------------------------------------------------------------
r235662 | thomas.stellard | 2015-04-23 18:59:24 -0400 (Thu, 23 Apr 2015) | 2 lines

R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236450 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r235641:
Tom Stellard [Mon, 4 May 2015 19:50:13 +0000 (19:50 +0000)]
Merging r235641:

------------------------------------------------------------------------
r235641 | thomas.stellard | 2015-04-23 16:32:01 -0400 (Thu, 23 Apr 2015) | 9 lines

R600/SI: Fix indirect addressing with a negative constant offset

When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.

In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236449 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r235524:
Tom Stellard [Mon, 4 May 2015 19:50:11 +0000 (19:50 +0000)]
Merging r235524:

------------------------------------------------------------------------
r235524 | Matthew.Arsenault | 2015-04-22 13:10:44 -0400 (Wed, 22 Apr 2015) | 4 lines

R600: Fix always inline pass breaking noinline functions

No test since calls are not actually supported yet.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236448 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoGCOV: Fix ABI breakage from r236303
Tom Stellard [Mon, 4 May 2015 19:18:18 +0000 (19:18 +0000)]
GCOV: Fix ABI breakage from r236303

This effectively reverts the part of r236303, which added a new member
to the GCOVOptions and broke ABI compatibility with 3.6.0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236445 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Added release notes for 3.6.1.
Daniel Sanders [Mon, 4 May 2015 11:39:04 +0000 (11:39 +0000)]
[mips] Added release notes for 3.6.1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236417 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227574:
Tom Stellard [Sat, 2 May 2015 04:17:33 +0000 (04:17 +0000)]
Merging r227574:

------------------------------------------------------------------------
r227574 | geek4civic | 2015-01-30 08:01:19 -0500 (Fri, 30 Jan 2015) | 2 lines

[Cygming] Seek also chkstk_ms, or JIT fails with DLL builds. It is fixup for r227519.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236379 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227519:
Tom Stellard [Sat, 2 May 2015 04:17:29 +0000 (04:17 +0000)]
Merging r227519:

------------------------------------------------------------------------
r227519 | reid | 2015-01-29 18:58:04 -0500 (Thu, 29 Jan 2015) | 10 lines

x86: Fix large model calls to __chkstk for dynamic allocas

In the large code model, we now put __chkstk in %r11 before calling it.

Refactor the code so that we only do this once. Simplify things by using
__chkstk_ms instead of __chkstk on cygming. We already use that symbol
in the prolog emission, and it simplifies our logic.

Second half of PR18582.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236378 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232443:
Tom Stellard [Fri, 1 May 2015 02:43:16 +0000 (02:43 +0000)]
Merging r232443:

------------------------------------------------------------------------
r232443 | mail | 2015-03-16 20:18:51 -0400 (Mon, 16 Mar 2015) | 4 lines

llvm-cov: Warn instead of error if a .gcda has arcs from an exit block

Patch by Vanderson M. Rosario. Thanks!

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236304 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232438:
Tom Stellard [Fri, 1 May 2015 02:43:13 +0000 (02:43 +0000)]
Merging r232438:

------------------------------------------------------------------------
r232438 | mail | 2015-03-16 19:52:03 -0400 (Mon, 16 Mar 2015) | 6 lines

GCOV: Make the exit block placement from r223193 optional

By default we want our gcov emission to stay 4.2 compatible, which
means we need to continue emit the exit block last by default. We add
an option to emit it before the body for users that need it.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236303 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227503:
Tom Stellard [Fri, 1 May 2015 02:43:11 +0000 (02:43 +0000)]
Merging r227503:

------------------------------------------------------------------------
r227503 | reid | 2015-01-29 17:33:00 -0500 (Thu, 29 Jan 2015) | 11 lines

Update comments to use unreachable instead of llvm.trap, as implemented now

win64: Call __chkstk through a register with the large code model

Fixes half of PR18582. True dynamic allocas will still have a
CALL64pcrel32 which will fail.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D7267

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236302 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r231259:
Tom Stellard [Thu, 30 Apr 2015 21:24:06 +0000 (21:24 +0000)]
Merging r231259:

------------------------------------------------------------------------
r231259 | marek.olsak | 2015-03-04 12:33:45 -0500 (Wed, 04 Mar 2015) | 4 lines

R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32

Required by OpenGL (ARB_gpu_shader5).

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236263 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r236099:
Daniel Sanders [Thu, 30 Apr 2015 09:21:49 +0000 (09:21 +0000)]
Merging r236099:
------------------------------------------------------------------------
r236099 | dsanders | 2015-04-29 13:28:58 +0100 (Wed, 29 Apr 2015) | 13 lines

[mips] Correct 128-bit shifts on 64-bit targets.

Summary:
The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
accounts for both cases.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits, mohit.bhakkad, sagar

Differential Revision: http://reviews.llvm.org/D9337
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236215 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCorrect syntax of getelementptr in regression test. NFC
Pawel Bylica [Wed, 29 Apr 2015 16:05:29 +0000 (16:05 +0000)]
Correct syntax of getelementptr in regression test. NFC

Bonus: unused variable removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236116 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAttempt #2: Fix ABI compatibility with 3.6.0 by moving new virtual function to end...
Daniel Sanders [Wed, 29 Apr 2015 15:29:14 +0000 (15:29 +0000)]
Attempt #2: Fix ABI compatibility with 3.6.0 by moving new virtual function to end of subclass. NFC

The previous attempt at fixing this only moved the problem to the subclass
vtable. We can safely move the function into the subclass so attempt to fix it
that way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236112 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerge r232176: ConstantFold: Fix big shift constant folding
Pawel Bylica [Wed, 29 Apr 2015 14:57:35 +0000 (14:57 +0000)]
Merge r232176: ConstantFold: Fix big shift constant folding

Constant folding for shift IR instructions ignores all bits above 32 of
second argument (shift amount).
Because of that, some undef results are not recognized and APInt can
raise an assert failure if second argument has more than 64 bits.

Patch by Paweł Bylica!

Differential Revision: http://reviews.llvm.org/D7701

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236109 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerge r231984: Handle big index in getelementptr instruction
Pawel Bylica [Wed, 29 Apr 2015 14:54:57 +0000 (14:54 +0000)]
Merge r231984: Handle big index in getelementptr instruction

CodeGen incorrectly ignores (assert from APInt) constant index bigger
than 2^64 in getelementptr instruction. This is a test and fix for that.

Patch by Paweł Bylica!

Reviewed By: rnk

Subscribers: majnemer, rnk, mcrosier, resistor, llvm-commits

Differential Revision: http://reviews.llvm.org/D8219

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236108 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix ABI compatibility with 3.6.0 by moving new virtual function to end of class....
Daniel Sanders [Wed, 29 Apr 2015 09:58:25 +0000 (09:58 +0000)]
Fix ABI compatibility with 3.6.0 by moving new virtual function to end of class. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236094 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r234891:
Tom Stellard [Wed, 29 Apr 2015 00:59:51 +0000 (00:59 +0000)]
Merging r234891:

------------------------------------------------------------------------
r234891 | thomas.stellard | 2015-04-14 10:36:45 -0400 (Tue, 14 Apr 2015) | 12 lines

R600/SI: Fix verifier error caused by SIAnnotateControlFlow

This pass will always try to insert llvm.SI.ifbreak intrinsics
in the same block that its conditional value is computed in.  This is
a problem when conditions for breaks or continue are computed outside
of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted
outside of the loop.

This patch fixes this problem by inserting the llvm.SI.ifbreak
intrinsics in the loop header when the condition is computed outside
the loop.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236072 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r233080:
Tom Stellard [Wed, 29 Apr 2015 00:59:49 +0000 (00:59 +0000)]
Merging r233080:

------------------------------------------------------------------------
r233080 | marek.olsak | 2015-03-24 09:40:38 -0400 (Tue, 24 Mar 2015) | 4 lines

R600/SI: Insert more NOPs after READLANE on VI, don't use NOPs on CI

This is a candidate for stable.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236071 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r233075:
Tom Stellard [Wed, 29 Apr 2015 00:59:47 +0000 (00:59 +0000)]
Merging r233075:

------------------------------------------------------------------------
r233075 | marek.olsak | 2015-03-24 09:40:08 -0400 (Tue, 24 Mar 2015) | 8 lines

R600/SI: Expand fract to floor, then only select V_FRACT on CI

V_FRACT is buggy on SI.

R600-specific code is left intact.

v2: drop the multiclass, use complex VOP3 patterns

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236070 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232957:
Tom Stellard [Wed, 29 Apr 2015 00:59:42 +0000 (00:59 +0000)]
Merging r232957:

------------------------------------------------------------------------
r232957 | thomas.stellard | 2015-03-23 12:06:01 -0400 (Mon, 23 Mar 2015) | 5 lines

R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()

This function assumed that SMRD instructions always have immediate
offsets, which is not always the case.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236069 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r234975:
Tom Stellard [Wed, 29 Apr 2015 00:41:57 +0000 (00:41 +0000)]
Merging r234975:

------------------------------------------------------------------------
r234975 | lhames | 2015-04-14 23:39:22 -0400 (Tue, 14 Apr 2015) | 5 lines

[RuntimeDyld] Make sure we emit MachO __eh_frame and __gcc_except_tab sections,
even if there are no references to them in the code.

This allows exceptions thrown from JIT'd code to be caught by the JIT itself.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236068 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r233410:
Tom Stellard [Wed, 29 Apr 2015 00:41:55 +0000 (00:41 +0000)]
Merging r233410:

------------------------------------------------------------------------
r233410 | ahmed.bougacha | 2015-03-27 16:35:49 -0400 (Fri, 27 Mar 2015) | 10 lines

[CodeGen] Don't attempt a tail-call with a non-forwarded explicit sret.

Tailcalls are only OK with forwarded sret pointers. With explicit sret,
one approximation is to check that the pointer isn't an Instruction, as
in that case it might point into some local memory (alloca). That's not
OK with tailcalls.

Explicit sret counterpart to r233409.
Differential Revison: http://reviews.llvm.org/D8510

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236067 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r233409:
Tom Stellard [Wed, 29 Apr 2015 00:41:53 +0000 (00:41 +0000)]
Merging r233409:

------------------------------------------------------------------------
r233409 | ahmed.bougacha | 2015-03-27 16:28:30 -0400 (Fri, 27 Mar 2015) | 7 lines

[CodeGen] Don't attempt a tail-call with implicit sret.

Tailcalls are only OK with forwarded sret pointers. With sret demotion,
they're not, as we'd have a pointer into a soon-to-be-dead stack frame.

Differential Revison: http://reviews.llvm.org/D8510

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236066 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232142:
Tom Stellard [Wed, 29 Apr 2015 00:41:51 +0000 (00:41 +0000)]
Merging r232142:

------------------------------------------------------------------------
r232142 | Hao.Liu | 2015-03-13 01:15:23 -0400 (Fri, 13 Mar 2015) | 9 lines

[MachineCopyPropagation] Fix a bug causing incorrect removal for the instruction sequences as follows
   %Q5_Q6<def> = COPY %Q2_Q3
   %D5<def> =
   %D3<def> =
   %D3<def> = COPY %D6     // Incorrectly removed in MachineCopyPropagation
   Using of %D3 results in incorrect result ...

   Reviewed in http://reviews.llvm.org/D8242

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236065 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMIPS: Fix test that uses 3.7 load syntax
Tom Stellard [Wed, 29 Apr 2015 00:41:48 +0000 (00:41 +0000)]
MIPS: Fix test that uses 3.7 load syntax

This was broken by r235973.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236064 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232797:
Tom Stellard [Tue, 28 Apr 2015 21:23:06 +0000 (21:23 +0000)]
Merging r232797:

------------------------------------------------------------------------
r232797 | thomas.stellard | 2015-03-19 23:12:42 -0400 (Thu, 19 Mar 2015) | 2 lines

R600/SI: Add missing CHECK-LABEL lines to a test

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236041 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232386:
Tom Stellard [Tue, 28 Apr 2015 21:23:04 +0000 (21:23 +0000)]
Merging r232386:

------------------------------------------------------------------------
r232386 | thomas.stellard | 2015-03-16 11:53:55 -0400 (Mon, 16 Mar 2015) | 8 lines

R600/SI: don't try min3/max3/med3 with f64

There are no opcodes for this. This also adds a test case.

v2: make test more robust

Patch by: Grigori Goronzy

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236040 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r231662:
Tom Stellard [Tue, 28 Apr 2015 21:23:02 +0000 (21:23 +0000)]
Merging r231662:

------------------------------------------------------------------------
r231662 | thomas.stellard | 2015-03-09 12:03:39 -0400 (Mon, 09 Mar 2015) | 2 lines

R600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236039 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r231659:
Tom Stellard [Tue, 28 Apr 2015 21:23:00 +0000 (21:23 +0000)]
Merging r231659:

------------------------------------------------------------------------
r231659 | marek.olsak | 2015-03-09 11:48:09 -0400 (Mon, 09 Mar 2015) | 4 lines

R600/SI: Limit SGPRs to 80 on Tonga and Iceland

This is a candidate for stable.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236038 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r231658:
Tom Stellard [Tue, 28 Apr 2015 21:22:56 +0000 (21:22 +0000)]
Merging r231658:

------------------------------------------------------------------------
r231658 | marek.olsak | 2015-03-09 11:48:00 -0400 (Mon, 09 Mar 2015) | 2 lines

R600/SI: Fix getNumSGPRsAllowed for VI

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236037 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230147:
Tom Stellard [Tue, 28 Apr 2015 19:12:20 +0000 (19:12 +0000)]
Merging r230147:

------------------------------------------------------------------------
r230147 | Matthew.Arsenault | 2015-02-21 16:29:04 -0500 (Sat, 21 Feb 2015) | 2 lines

R600/SI: Don't crash when getting immediate operand size

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236022 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230146:
Tom Stellard [Tue, 28 Apr 2015 19:12:19 +0000 (19:12 +0000)]
Merging r230146:

------------------------------------------------------------------------
r230146 | Matthew.Arsenault | 2015-02-21 16:29:00 -0500 (Sat, 21 Feb 2015) | 2 lines

R600/SI: Fix mad*k definitions

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236021 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229752:
Tom Stellard [Tue, 28 Apr 2015 19:12:16 +0000 (19:12 +0000)]
Merging r229752:

------------------------------------------------------------------------
r229752 | marek.olsak | 2015-02-18 17:12:45 -0500 (Wed, 18 Feb 2015) | 10 lines

R600/SI: Fix READLANE and WRITELANE lane select for VI

VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.

This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236020 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229751:
Tom Stellard [Tue, 28 Apr 2015 19:12:14 +0000 (19:12 +0000)]
Merging r229751:

------------------------------------------------------------------------
r229751 | marek.olsak | 2015-02-18 17:12:41 -0500 (Wed, 18 Feb 2015) | 2 lines

R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_C

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236019 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229750:
Tom Stellard [Tue, 28 Apr 2015 19:12:12 +0000 (19:12 +0000)]
Merging r229750:

------------------------------------------------------------------------
r229750 | marek.olsak | 2015-02-18 17:12:37 -0500 (Wed, 18 Feb 2015) | 4 lines

R600/SI: Remove explicit VOP operand checking

This should be handled by the OperandType checking.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236018 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229507:
Tom Stellard [Tue, 28 Apr 2015 19:12:11 +0000 (19:12 +0000)]
Merging r229507:

------------------------------------------------------------------------
r229507 | thomas.stellard | 2015-02-17 11:36:00 -0500 (Tue, 17 Feb 2015) | 2 lines

R600/SI: Extend private extload pattern to include zext loads

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236017 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229239:
Tom Stellard [Tue, 28 Apr 2015 19:12:08 +0000 (19:12 +0000)]
Merging r229239:

------------------------------------------------------------------------
r229239 | Matthew.Arsenault | 2015-02-13 23:30:08 -0500 (Fri, 13 Feb 2015) | 4 lines

R600/SI: Implement correct f64 fdiv

This version passes the OpenCL conformance test.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236016 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232943:
Daniel Sanders [Tue, 28 Apr 2015 09:39:55 +0000 (09:39 +0000)]
Merging r232943:
------------------------------------------------------------------------
r232943 | petarj | 2015-03-23 12:28:13 +0000 (Mon, 23 Mar 2015) | 10 lines

Fix sign extension for MIPS64 in makeLibCall function

Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all
32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign
extended. This fixes test "MultiSource/Applications/oggenc/".

Patch by Strahinja Petrovic.

Differential Revision: http://reviews.llvm.org/D7791

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235973 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228765:
Daniel Sanders [Tue, 28 Apr 2015 09:39:13 +0000 (09:39 +0000)]
Merging r228765:
------------------------------------------------------------------------
r228765 | petarj | 2015-02-10 23:30:14 +0000 (Tue, 10 Feb 2015) | 12 lines

Fix makeLibCall argument (signed) in SoftenFloatRes_XINT_TO_FP function

The isSigned argument of makeLibCall function was hard-coded to false
(unsigned). This caused zero extension on MIPS64 soft float.
As the result SingleSource/Benchmarks/Stanford/FloatMM test and
SingleSource/UnitTests/2005-07-17-INT-To-FP test failed.
The solution was to use the proper argument.

Patch by Strahinja Petrovic.

Differential Revision: http://reviews.llvm.org/D7292

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235972 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r231237:
Daniel Sanders [Mon, 27 Apr 2015 15:07:42 +0000 (15:07 +0000)]
Merging r231237:
------------------------------------------------------------------------
r231237 | vkalintiris | 2015-03-04 12:10:18 +0000 (Wed, 04 Mar 2015) | 6 lines

[mips] Specify the correct value type when combining a CMovFP node.

This commit fixes a bug introduced in r230956 where we were creating
CMovFP_{T,F} nodes with multiple return value types (one for each operand).
With this change the return value type of the new node is the same as the
value type of the True/False operands of the original node.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235888 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230956:
Daniel Sanders [Mon, 27 Apr 2015 14:57:52 +0000 (14:57 +0000)]
Merging r230956:
------------------------------------------------------------------------
r230956 | vkalintiris | 2015-03-02 12:47:32 +0000 (Mon, 02 Mar 2015) | 10 lines

[mips] Optimize conditional moves where RHS is zero.

Summary:
When the RHS of a conditional move node is zero, we can utilize the $zero
register by inverting the conditional move instruction and by swapping the
order of its True/False operands.

Reviewers: dsanders

Differential Revision: http://reviews.llvm.org/D7945
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235886 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230500:
Daniel Sanders [Mon, 27 Apr 2015 14:50:09 +0000 (14:50 +0000)]
Merging r230500:
------------------------------------------------------------------------
r230500 | vmedic | 2015-02-25 15:24:37 +0000 (Wed, 25 Feb 2015) | 1 line

[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235885 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228403:
Daniel Sanders [Mon, 27 Apr 2015 14:41:51 +0000 (14:41 +0000)]
Merging r228403:
------------------------------------------------------------------------
r228403 | dsanders | 2015-02-06 16:37:30 +0000 (Fri, 06 Feb 2015) | 2 lines

[mips] Fix FileCheck prefixes with whitespace between 'CHECK' and ':'

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235884 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r233904:
Daniel Sanders [Mon, 27 Apr 2015 14:31:46 +0000 (14:31 +0000)]
Merging r233904:
------------------------------------------------------------------------
r233904 | vkalintiris | 2015-04-02 11:14:54 +0100 (Thu, 02 Apr 2015) | 9 lines

[mips] Make sure that we don't adjust the stack pointer by zero amount.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8638
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235883 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r232382:
Daniel Sanders [Mon, 27 Apr 2015 13:36:41 +0000 (13:36 +0000)]
Merging r232382:
------------------------------------------------------------------------
r232382 | petarj | 2015-03-16 15:01:09 +0000 (Mon, 16 Mar 2015) | 13 lines

[MIPS] Fix justify error for small structures

Fix justify error for small structures bigger than 32 bits in fixed
arguments for MIPS64 big endian. There was a problem when small structures
are passed as fixed arguments. The structures that are bigger than 32 bits
but smaller than 64 bits were not left justified properly on MIPS64 big
endian. This is fixed by shifting the value to make it left justified when
appropriate.

Patch by Aleksandar Beserminji.

Differential Revision: http://reviews.llvm.org/D8174

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235879 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230748:
Daniel Sanders [Mon, 27 Apr 2015 13:07:43 +0000 (13:07 +0000)]
Merging r230748:
------------------------------------------------------------------------
r230748 | tomatabacu | 2015-02-27 10:44:02 +0000 (Fri, 27 Feb 2015) | 11 lines

[mips] Remove redundant periods from -mattr=help descriptions for MIPS.

Summary: Also fixes an infringement of the 80-column limit rule.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7910
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235876 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230742:
Daniel Sanders [Mon, 27 Apr 2015 12:56:05 +0000 (12:56 +0000)]
Merging r230742:
------------------------------------------------------------------------
r230742 | vkalintiris | 2015-02-27 09:01:39 +0000 (Fri, 27 Feb 2015) | 12 lines

[mips] Account for constant-zero operands in ADDE nodes.

Summary:
We identify the cases where the operand to an ADDE node is a constant
zero. In such cases, we can avoid generating an extra ADDu instruction
disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r).

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7906
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235874 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230657:
Daniel Sanders [Mon, 27 Apr 2015 12:22:47 +0000 (12:22 +0000)]
Merging r230657:
------------------------------------------------------------------------
r230657 | petarj | 2015-02-26 18:35:15 +0000 (Thu, 26 Feb 2015) | 13 lines

Fix justify error for small structures in varargs for MIPS64BE

There was a problem when passing structures as variable arguments.
The structures smaller than 64 bit were not left justified on MIPS64
big endian. This is now fixed by shifting the value to make it left-
justified when appropriate.

This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608

Patch by Aleksandar Beserminji.

Differential Revision: http://reviews.llvm.org/D7881

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235872 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r230235:
Daniel Sanders [Mon, 27 Apr 2015 12:15:29 +0000 (12:15 +0000)]
Merging r230235:
------------------------------------------------------------------------
r230235 | dsanders | 2015-02-23 17:22:16 +0000 (Mon, 23 Feb 2015) | 16 lines

[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.

Summary:
-mno-odd-spreg prohibits the use of odd-numbered single-precision floating
point registers. However, vector insert/extract was still using them when
manipulating the subregisters of an MSA register. Fixed this by ensuring
that insertion/extraction is only performed on even-numbered vector
registers when -mno-odd-spreg is given.

Reviewers: vmedic, sstankovic

Reviewed By: sstankovic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7672
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235870 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229675:
Daniel Sanders [Mon, 27 Apr 2015 12:08:26 +0000 (12:08 +0000)]
Merging r229675:
------------------------------------------------------------------------
r229675 | vkalintiris | 2015-02-18 14:57:05 +0000 (Wed, 18 Feb 2015) | 7 lines

[mips] Avoid redundant sign extension of the result of binary bitwise instructions.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7581
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235869 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227430:
Daniel Sanders [Mon, 27 Apr 2015 11:59:49 +0000 (11:59 +0000)]
Merging r227430:
------------------------------------------------------------------------
r227430 | vmedic | 2015-01-29 11:33:41 +0000 (Thu, 29 Jan 2015) | 1 line

[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235864 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227084:
Daniel Sanders [Mon, 27 Apr 2015 10:29:59 +0000 (10:29 +0000)]
Merging r227084:
------------------------------------------------------------------------
r227084 | vmedic | 2015-01-26 10:33:43 +0000 (Mon, 26 Jan 2015) | 1 line

When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235859 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227269:
Daniel Sanders [Mon, 27 Apr 2015 10:20:08 +0000 (10:20 +0000)]
Merging r227269:
------------------------------------------------------------------------
r227269 | petarj | 2015-01-27 23:30:18 +0000 (Tue, 27 Jan 2015) | 7 lines

[mips] Use __clear_cache builtin instead of cacheflush()

Use __clear_cache builtin instead of cacheflush() in
Unix Memory::InvalidateInstructionCache().

Differential Revision: http://reviews.llvm.org/D7198

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235858 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226905:
Daniel Sanders [Mon, 27 Apr 2015 09:44:39 +0000 (09:44 +0000)]
Merging r226905:
------------------------------------------------------------------------
r226905 | tomatabacu | 2015-01-23 10:40:19 +0000 (Fri, 23 Jan 2015) | 18 lines

[mips] Add new error message and improve testing for parsing the .module directive.

Summary:
We used to silently ignore any empty .module's and we used to give an error saying that we found
an "unexpected token at start of statement" when the value of the option wasn't an identifier (e.g. if it was a number).

We now give an error saying that we "expected .module option identifier" in both of those cases.

I also fixed the other tests in mips-abi-bad.s, which all seemed to be broken.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7095
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235856 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226652:
Daniel Sanders [Mon, 27 Apr 2015 09:42:44 +0000 (09:42 +0000)]
Merging r226652:
------------------------------------------------------------------------
r226652 | vmedic | 2015-01-21 10:47:36 +0000 (Wed, 21 Jan 2015) | 1 line

[Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235855 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226409:
Daniel Sanders [Mon, 27 Apr 2015 08:55:45 +0000 (08:55 +0000)]
Merging r226409:
------------------------------------------------------------------------
r226409 | dsanders | 2015-01-18 18:43:10 +0000 (Sun, 18 Jan 2015) | 2 lines

[mips] 'CHECK :' is not a valid check directive. Fixed.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235850 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226408:
Daniel Sanders [Mon, 27 Apr 2015 08:53:54 +0000 (08:53 +0000)]
Merging r226408:
------------------------------------------------------------------------
r226408 | dsanders | 2015-01-18 18:38:36 +0000 (Sun, 18 Jan 2015) | 9 lines

[mips] Make whitespace in disassembler tests more consistent. NFC.

The tests for the ISA's should now be approximately diffable. That is, the
output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines
for instructions that were added/removed to/from MIPS-I by MIPS-II. This
doesn't work perfectly at the moment due to ordering differences but it
should be close.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235849 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226407:
Daniel Sanders [Mon, 27 Apr 2015 08:52:15 +0000 (08:52 +0000)]
Merging r226407:
------------------------------------------------------------------------
r226407 | dsanders | 2015-01-18 18:21:19 +0000 (Sun, 18 Jan 2015) | 3 lines

[mips] Make whitespace of disassembler tests more consistent by removing blank lines. NFC.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235848 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226166:
Daniel Sanders [Mon, 27 Apr 2015 08:51:28 +0000 (08:51 +0000)]
Merging r226166:
------------------------------------------------------------------------
r226166 | vmedic | 2015-01-15 14:18:12 +0000 (Thu, 15 Jan 2015) | 1 line

Add disassembler tests for mips64r6 platform. There are no functional changes.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235847 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226165:
Daniel Sanders [Mon, 27 Apr 2015 08:50:58 +0000 (08:50 +0000)]
Merging r226165:
------------------------------------------------------------------------
r226165 | vmedic | 2015-01-15 14:11:38 +0000 (Thu, 15 Jan 2015) | 1 line

Add disassembler tests for mips32r6 platform. There are no functional changes.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235846 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226164:
Daniel Sanders [Mon, 27 Apr 2015 08:50:30 +0000 (08:50 +0000)]
Merging r226164:
------------------------------------------------------------------------
r226164 | vmedic | 2015-01-15 14:06:34 +0000 (Thu, 15 Jan 2015) | 1 line

Add disassembler tests for mips64r2 platform. There are no functional changes.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235845 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r226151:
Daniel Sanders [Mon, 27 Apr 2015 08:49:48 +0000 (08:49 +0000)]
Merging r226151:
------------------------------------------------------------------------
r226151 | vmedic | 2015-01-15 08:50:20 +0000 (Thu, 15 Jan 2015) | 1 line

Add disassembler tests for mips64 platform. There are no functional changes.
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235844 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229238:
Tom Stellard [Fri, 24 Apr 2015 01:30:56 +0000 (01:30 +0000)]
Merging r229238:

------------------------------------------------------------------------
r229238 | Matthew.Arsenault | 2015-02-13 23:24:28 -0500 (Fri, 13 Feb 2015) | 2 lines

R600/SI: Use complex operand folding for div_scale

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235686 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229236:
Tom Stellard [Fri, 24 Apr 2015 01:30:54 +0000 (01:30 +0000)]
Merging r229236:

------------------------------------------------------------------------
r229236 | Matthew.Arsenault | 2015-02-13 23:22:00 -0500 (Fri, 13 Feb 2015) | 7 lines

R600/SI: Fix implicit vcc operand to v_div_fmas_*

This should allow finally fixing the f64 fdiv implementation.

Test is disabled for VI since there seems to be a problem with one
of the buffer load instructions on it.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235685 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229235:
Tom Stellard [Fri, 24 Apr 2015 01:30:51 +0000 (01:30 +0000)]
Merging r229235:

------------------------------------------------------------------------
r229235 | Matthew.Arsenault | 2015-02-13 23:03:18 -0500 (Fri, 13 Feb 2015) | 2 lines

R600/SI: Fix schedule model for v_div_scale_{f32|f64}

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235684 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229234:
Tom Stellard [Fri, 24 Apr 2015 01:30:49 +0000 (01:30 +0000)]
Merging r229234:

------------------------------------------------------------------------
r229234 | Matthew.Arsenault | 2015-02-13 22:54:32 -0500 (Fri, 13 Feb 2015) | 2 lines

R600/SI: Really fix size of VReg_1

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235683 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229230:
Tom Stellard [Fri, 24 Apr 2015 01:05:03 +0000 (01:05 +0000)]
Merging r229230:

------------------------------------------------------------------------
r229230 | Matthew.Arsenault | 2015-02-13 22:40:35 -0500 (Fri, 13 Feb 2015) | 4 lines

R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}

This apparently got lost in the VI changes.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235678 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229228:
Tom Stellard [Thu, 23 Apr 2015 19:14:45 +0000 (19:14 +0000)]
Merging r229228:

------------------------------------------------------------------------
r229228 | Matthew.Arsenault | 2015-02-13 22:02:23 -0500 (Fri, 13 Feb 2015) | 2 lines

R600/SI: Fix VOP3b encoding on VI

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235625 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229227:
Tom Stellard [Thu, 23 Apr 2015 19:14:43 +0000 (19:14 +0000)]
Merging r229227:

------------------------------------------------------------------------
r229227 | Matthew.Arsenault | 2015-02-13 21:55:57 -0500 (Fri, 13 Feb 2015) | 2 lines

R600/SI: Fix phys reg copies in SIFoldOperands

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235624 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229226:
Tom Stellard [Thu, 23 Apr 2015 19:14:42 +0000 (19:14 +0000)]
Merging r229226:

------------------------------------------------------------------------
r229226 | Matthew.Arsenault | 2015-02-13 21:55:56 -0500 (Fri, 13 Feb 2015) | 5 lines

R600/SI: Fix copies from SGPR to VCC

This shows up without optimizations when vcc is required
to be used.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235623 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229225:
Tom Stellard [Thu, 23 Apr 2015 19:14:40 +0000 (19:14 +0000)]
Merging r229225:

------------------------------------------------------------------------
r229225 | Matthew.Arsenault | 2015-02-13 21:55:54 -0500 (Fri, 13 Feb 2015) | 4 lines

R600/SI: Add hack to copy from a VGPR to VCC

This hopefully should be fixed when VReg_1 is removed.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235622 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r229223:
Tom Stellard [Thu, 23 Apr 2015 19:14:38 +0000 (19:14 +0000)]
Merging r229223:

------------------------------------------------------------------------
r229223 | Matthew.Arsenault | 2015-02-13 21:51:44 -0500 (Fri, 13 Feb 2015) | 5 lines

R600/SI: Fix size of VReg_1

This is really a 32-bit register, if we try to check the size of it,
we want 32-bits.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235621 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228848:
Tom Stellard [Wed, 22 Apr 2015 21:13:11 +0000 (21:13 +0000)]
Merging r228848:

------------------------------------------------------------------------
r228848 | thomas.stellard | 2015-02-11 12:11:48 -0500 (Wed, 11 Feb 2015) | 2 lines

R600/SI: Fix -march in test

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235550 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228374:
Tom Stellard [Wed, 22 Apr 2015 21:13:10 +0000 (21:13 +0000)]
Merging r228374:

------------------------------------------------------------------------
r228374 | michel.daenzer | 2015-02-05 21:51:29 -0500 (Thu, 05 Feb 2015) | 4 lines

R600/SI: Amend a test to ensure WQM is enabled for LDS in pixel shaders

Reviewed-by: Tom Stellard <tom@stellard.net>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235549 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228373:
Tom Stellard [Wed, 22 Apr 2015 21:13:09 +0000 (21:13 +0000)]
Merging r228373:

------------------------------------------------------------------------
r228373 | michel.daenzer | 2015-02-05 21:51:25 -0500 (Thu, 05 Feb 2015) | 8 lines

R600/SI: Don't enable WQM for V_INTERP_* instructions v2

Doesn't seem necessary anymore. I think this was mostly compensating for
not enabling WQM for texture sampling instructions.

v2: Add test coverage
Reviewed-by: Tom Stellard <tom@stellard.net>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235548 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228372:
Tom Stellard [Wed, 22 Apr 2015 21:13:07 +0000 (21:13 +0000)]
Merging r228372:

------------------------------------------------------------------------
r228372 | michel.daenzer | 2015-02-05 21:51:20 -0500 (Thu, 05 Feb 2015) | 12 lines

R600/SI: Also enable WQM for image opcodes which calculate LOD v3

If whole quad mode isn't enabled for these, the level of detail is
calculated incorrectly for pixels along diagonal triangle edges, causing
artifacts.

v2: Use a TSFlag instead of lots of switch cases
v3: Add test coverage

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
Reviewed-by: Tom Stellard <tom@stellard.net>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235547 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228273:
Tom Stellard [Wed, 22 Apr 2015 21:13:04 +0000 (21:13 +0000)]
Merging r228273:

------------------------------------------------------------------------
r228273 | Matthew.Arsenault | 2015-02-05 01:05:13 -0500 (Thu, 05 Feb 2015) | 2 lines

R600/SI: Fix i64 truncate to i1

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235546 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228190:
Tom Stellard [Mon, 20 Apr 2015 20:05:00 +0000 (20:05 +0000)]
Merging r228190:

------------------------------------------------------------------------
r228190 | thomas.stellard | 2015-02-04 15:49:52 -0500 (Wed, 04 Feb 2015) | 2 lines

R600/SI: Expand misaligned 16-bit memory accesses

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235340 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228189:
Tom Stellard [Mon, 20 Apr 2015 20:04:59 +0000 (20:04 +0000)]
Merging r228189:

------------------------------------------------------------------------
r228189 | thomas.stellard | 2015-02-04 15:49:51 -0500 (Wed, 04 Feb 2015) | 9 lines

R600/SI: Make more store operations legal

v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for
all address spaces.  We had marked them as custom in order to lower
them for the private address space, but this is no longer necessary.

This enables lowering of misaligned stores of these types in the
DAGLegalizer.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235339 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228188:
Tom Stellard [Mon, 20 Apr 2015 20:04:57 +0000 (20:04 +0000)]
Merging r228188:

------------------------------------------------------------------------
r228188 | thomas.stellard | 2015-02-04 15:49:49 -0500 (Wed, 04 Feb 2015) | 5 lines

R600: Don't promote i64 stores to v2i32 during DAG legalization

We take care of this during instruction selection now.  This
fixes a potential infinite loop when lowering misaligned stores.

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235338 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228040:
Tom Stellard [Mon, 20 Apr 2015 20:04:54 +0000 (20:04 +0000)]
Merging r228040:

------------------------------------------------------------------------
r228040 | marek.olsak | 2015-02-03 16:53:27 -0500 (Tue, 03 Feb 2015) | 2 lines

R600/SI: Remove the -CHECK suffix from all FileCheck prefixes in LIT
tests

------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235337 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228039:
Tom Stellard [Mon, 20 Apr 2015 20:04:48 +0000 (20:04 +0000)]
Merging r228039:

------------------------------------------------------------------------
r228039 | marek.olsak | 2015-02-03 16:53:08 -0500 (Tue, 03 Feb 2015) | 6 lines

R600/SI: Remove useless patterns in VALU which are already covered by SALU

Also remove hasPostISelHook=1 from V_LSHL_B32. It's defined by InstSI already.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235336 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228038:
Tom Stellard [Mon, 20 Apr 2015 18:06:16 +0000 (18:06 +0000)]
Merging r228038:

------------------------------------------------------------------------
r228038 | marek.olsak | 2015-02-03 16:53:05 -0500 (Tue, 03 Feb 2015) | 10 lines

R600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcode

What this does is that if you accidentally select these instructions on VI,
the code generation will fail, because the pseudo -> _vi mapping will be
undefined.

The idea is to be able to catch possible future bugs easily.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235319 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r228037:
Tom Stellard [Mon, 20 Apr 2015 18:06:14 +0000 (18:06 +0000)]
Merging r228037:

------------------------------------------------------------------------
r228037 | marek.olsak | 2015-02-03 16:53:01 -0500 (Tue, 03 Feb 2015) | 6 lines

R600/SI: Fix B64 VALU shifts on VI

SI only has standard versions. VI only has REV versions.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235318 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227990:
Tom Stellard [Mon, 20 Apr 2015 18:06:11 +0000 (18:06 +0000)]
Merging r227990:

------------------------------------------------------------------------
r227990 | marek.olsak | 2015-02-03 12:38:12 -0500 (Tue, 03 Feb 2015) | 14 lines

R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI

This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235317 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227989:
Tom Stellard [Mon, 20 Apr 2015 18:06:09 +0000 (18:06 +0000)]
Merging r227989:

------------------------------------------------------------------------
r227989 | marek.olsak | 2015-02-03 12:38:05 -0500 (Tue, 03 Feb 2015) | 10 lines

R600/SI: Remove VOP2_REV definitions from target-specific instructions

The getCommute* functions are only used with pseudos, so this commit doesn't
change anything.

The issue with missing non-rev versions of shift instructions on VI will fixed
separately.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235316 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227988:
Tom Stellard [Mon, 20 Apr 2015 18:06:07 +0000 (18:06 +0000)]
Merging r227988:

------------------------------------------------------------------------
r227988 | marek.olsak | 2015-02-03 12:38:01 -0500 (Tue, 03 Feb 2015) | 11 lines

R600/SI: Trivial instruction definition corrections for VI (v2)

- V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only.

- Define CVT_PK opcodes which are different between SI and VI. These are
  unused. The idea is to define all chip differences.

v2: keep V_MUL_LO_U32

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235315 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227987:
Tom Stellard [Fri, 17 Apr 2015 16:59:33 +0000 (16:59 +0000)]
Merging r227987:

------------------------------------------------------------------------
r227987 | marek.olsak | 2015-02-03 12:37:57 -0500 (Tue, 03 Feb 2015) | 12 lines

R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2

These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can
be a problem. In order to make isVOP2 and isVOP3 queries behave as expected,
the encoding must be determined first.

This doesn't fix any known issue, but better safe than sorry.

v2: add and use getMCOpcodeFromPseudo

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235208 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMerging r227986:
Tom Stellard [Fri, 17 Apr 2015 16:59:32 +0000 (16:59 +0000)]
Merging r227986:

------------------------------------------------------------------------
r227986 | marek.olsak | 2015-02-03 12:37:52 -0500 (Tue, 03 Feb 2015) | 9 lines

R600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2)

This fixes a hang when using an empty geometry shader.

v2: - don't add s_nop when followed by s_waitcnt
    - comestic changes

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
------------------------------------------------------------------------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235207 91177308-0d34-0410-b5e6-96231b3b80d8