Matt Arsenault [Tue, 2 Jul 2019 14:16:39 +0000 (14:16 +0000)]
GlobalISel: Add G_FENCE
The pattern importer is for some reason emitting checks for G_CONSTANT
for the immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364926
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Simon Pilgrim [Tue, 2 Jul 2019 13:30:04 +0000 (13:30 +0000)]
[X86][AVX] combineX86ShuffleChain - pull out CombineShuffleWithExtract lambda. NFCI.
Pull out CombineShuffleWithExtract lambda to new combineX86ShuffleChainWithExtract wrapper and refactored it to handle more than 2 shuffle inputs - this will allow combineX86ShufflesRecursively to call this in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364924
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Kristof Umann [Tue, 2 Jul 2019 13:25:41 +0000 (13:25 +0000)]
Removed extra ; after function definition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364923
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Roman Lebedev [Tue, 2 Jul 2019 13:21:23 +0000 (13:21 +0000)]
[NFC][TargetLowering] Some preparatory cleanups around 'prepareUREMEqFold()' from D63963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364921
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Roman Lebedev [Tue, 2 Jul 2019 13:21:17 +0000 (13:21 +0000)]
[APIntTest] multiplicativeInverse(): clarify test
Clarify that multiplicative inverse exists for all odd numbers,
and does not exist for all even numbers (including 0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364920
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Paul Robinson [Tue, 2 Jul 2019 13:13:36 +0000 (13:13 +0000)]
Fix line endings (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364919
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James Henderson [Tue, 2 Jul 2019 13:11:34 +0000 (13:11 +0000)]
[docs][llvm-readelf] Delete old llvm-readelf.md
This was accidentally missed when committing r364800.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364918
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George Rimar [Tue, 2 Jul 2019 12:58:37 +0000 (12:58 +0000)]
[Object/invalid.test] - Convert Object/corrupt.test to YAML and merge the result into invalid.test
Object/corrupt.test has the same purpose as Object/invalid.test:
it tests the behavior on invalid inputs.
In this patch I converted it to YAML, merged into invalid.test,
added comments and removed a few precompiled binaries.
Differential revision: https://reviews.llvm.org/D63927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364916
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Roman Lebedev [Tue, 2 Jul 2019 12:54:48 +0000 (12:54 +0000)]
[InstCombine] Shift amount reassociation: fixup constantexpr handling (PR42484)
I was actually wondering if there was some nicer way than m_Value()+cast,
but apparently what i was really "subconsciously" thinking about
was correctness issue.
hasNoUnsignedWrap()/hasNoUnsignedWrap() exist for Instruction,
not for BinaryOperator, so let's just use m_Instruction(),
thus both avoiding a cast, and a crash.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42484,
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364915
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Kristof Umann [Tue, 2 Jul 2019 12:40:29 +0000 (12:40 +0000)]
Attempt to fix buildbot failures with MSVC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364914
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Michal Gorny [Tue, 2 Jul 2019 11:32:03 +0000 (11:32 +0000)]
[llvm] [Support] Clean PrintStackTrace() ptr arithmetic up
Use '%tu' modifier for pointer arithmetic since we are using C++11
already. Prefer static_cast<> over C-style cast. Remove unnecessary
conversion of result, and add const qualifier to converted pointers,
to silence the following warning:
In file included from /home/mgorny/llvm-project/llvm/lib/Support/Signals.cpp:220:0:
/home/mgorny/llvm-project/llvm/lib/Support/Unix/Signals.inc: In function ‘void llvm::sys::PrintStackTrace(llvm::raw_ostream&)’:
/home/mgorny/llvm-project/llvm/lib/Support/Unix/Signals.inc:546:53: warning: cast from type ‘const void*’ to type ‘char*’ casts away qualifiers [-Wcast-qual]
(char*)dlinfo.dli_saddr));
^~~~~~~~~
Differential Revision: https://reviews.llvm.org/D63888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364912
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Kristof Umann [Tue, 2 Jul 2019 11:30:12 +0000 (11:30 +0000)]
[IDF] Generalize IDFCalculator to be used with Clang's CFG
I'm currently working on a GSoC project that aims to improve the the bug reports
of the analyzer. The main heuristic I plan to use is to explain values that are
a control dependency of the bug location better.
01 bool b = messyComputation();
02 int i = 0;
03 if (b) // control dependency of the bug site, let's explain why we assume val
04 // to be true
05 10 / i; // warn: division by zero
Because of this, I'd like to generalize IDFCalculator so that I could use it for
Clang's CFG: D62883.
In detail:
* Rename IDFCalculator to IDFCalculatorBase, make it take a general CFG node
type as a template argument rather then strictly BasicBlock (but preserve
ForwardIDFCalculator and ReverseIDFCalculator)
* Move IDFCalculatorBase from llvm/include/llvm/Analysis to
llvm/include/llvm/Support (but leave the BasicBlock variants in
llvm/include/llvm/Analysis)
* clang-format the file since this patch messes up git blame anyways
* Change typedef to using
* Add the new type ChildrenGetterTy, and store an instance of it in
IDFCalculatorBase. This is important because I'll have to specialize it for
Clang's CFG to filter out nullpointer successors, similarly to D62507.
Differential Revision: https://reviews.llvm.org/D63389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364911
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Simon Tatham [Tue, 2 Jul 2019 11:26:11 +0000 (11:26 +0000)]
[ARM] MVE: allow soft-float ABI to pass vector types.
Passing a vector type over the soft-float ABI involves it being split
into four GPRs, so the first thing that has to happen at the start of
the function is to recombine those into a vector register. The ABI
types all vectors as v2f64, so we need to support BUILD_VECTOR for
that type, which I do in this patch by allowing it to be expanded in
terms of INSERT_VECTOR_ELT, and writing an ISel pattern for that in
turn. Similarly, I provide a rule for EXTRACT_VECTOR_ELT so that a
returned vector can be marshalled back into GPRs.
While I'm here, I've also added ISD::UNDEF to the list of operations
we turn back on in `setAllExpand`, because I noticed that otherwise it
gets expanded into a BUILD_VECTOR with explicit zero inputs, leading
to pointless machine instructions to zero out a vector register that's
about to have every lane overwritten of in any case.
Reviewers: dmgreen, ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364910
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Simon Tatham [Tue, 2 Jul 2019 11:26:00 +0000 (11:26 +0000)]
[ARM] Stop using scalar FP instructions in integer-only MVE mode.
If you compile with `-mattr=+mve` (enabling integer MVE instructions
but not floating-point ones), then the scalar FP //registers// exist
and it's legal to move things in and out of them, load and store them,
but it's not legal to do arithmetic on them.
In D60708, the calls to `addRegisterClass` in ARMISelLowering that
enable use of the scalar FP registers became conditionalised on
`Subtarget->hasFPRegs()` instead of `Subtarget->hasVFP2Base()`, so
that loads, stores and moves of those registers would work. But I
didn't realise that that would also enable all the operations on those
types by default.
Now, if the target doesn't have basic VFP, we follow up those
`addRegisterClass` calls by turning back off all the nontrivial
operations you can perform on f32 and f64. That causes several
knock-on failures, which are fixed by allowing the `VMOVDcc` and
`VMOVScc` instructions to be selected even if all you have is
`HasFPRegs`, and adjusting several checks for 'is this a double in a
single-precision-only world?' to the more general 'is this any FP type
we can't do arithmetic on?'. Between those, the whole of the
`float-ops.ll` and `fp16-instructions.ll` tests can now run in
MVE-without-FP mode and generate correct-looking code.
One odd side effect is that I had to relax the check lines in that
test so that they permit test functions like `add_f` to be generated
as tailcalls to software FP library functions, instead of ordinary
calls. Doing that is entirely legal, but the mystery is why this is
the first RUN line that's needed the relaxation: on the usual kind of
non-FP target, no tailcalls ever seem to be generated. Going by the
llc messages, I think `SoftenFloatResult` must be perturbing the code
generation in some way, but that's as much as I can guess.
Reviewers: dmgreen, ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364909
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Nico Weber [Tue, 2 Jul 2019 11:20:40 +0000 (11:20 +0000)]
gn build: Merge r364866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364908
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George Rimar [Tue, 2 Jul 2019 11:02:09 +0000 (11:02 +0000)]
[yaml2obj] - An attempt to fix a ppc64be build bot after r364898
I guess the problem is because of endianess of
the bytes tested by "od" tool. I changed the Content
sequence as it does not actually matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364907
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Simon Pilgrim [Tue, 2 Jul 2019 10:53:17 +0000 (10:53 +0000)]
[X86] resolveTargetShuffleInputsAndMask - add repeated input handling.
We were relying on combineX86ShufflesRecursively to handle this - this patch gets it done earlier which should make it easier for other code to use resolveTargetShuffleInputsAndMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364906
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George Rimar [Tue, 2 Jul 2019 10:47:13 +0000 (10:47 +0000)]
[test/Object] - Fix build bot.
Fixed mistype in the test case.
BB: http://lab.llvm.org:8011/builders/lld-x86_64-ubuntu-fast/builds/2720/steps/test-check-all/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364905
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George Rimar [Tue, 2 Jul 2019 10:30:06 +0000 (10:30 +0000)]
[Object/invalid.test] - Convert 3 more sub-tests to YAML
This allows to remove 3 more precompiled binaries from the inputs.
Differential revision: https://reviews.llvm.org/D63880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364903
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Simon Atanasyan [Tue, 2 Jul 2019 10:22:14 +0000 (10:22 +0000)]
[mips] Mark P5600 scheduling model as complete
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364902
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Simon Atanasyan [Tue, 2 Jul 2019 10:22:06 +0000 (10:22 +0000)]
[mips] Add missing schedinfo for FPU load/store/conv instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364900
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Simon Atanasyan [Tue, 2 Jul 2019 10:21:59 +0000 (10:21 +0000)]
[mips] Map SNOP, NOP to the P5600Nop scheduler resource
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364899
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George Rimar [Tue, 2 Jul 2019 10:20:12 +0000 (10:20 +0000)]
[yaml2obj] - Allow overriding sh_offset field from the YAML.
Some of our test cases are using objects which
has sections with a broken sh_offset field.
There was no way to set it from YAML until this patch.
Differential revision: https://reviews.llvm.org/D63879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364898
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Roman Lebedev [Tue, 2 Jul 2019 10:02:25 +0000 (10:02 +0000)]
[NFC][InstCombine] Revisit tests for "redundant shift input masking" (PR42456)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364897
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Igor Kudrin [Tue, 2 Jul 2019 09:57:28 +0000 (09:57 +0000)]
[DWARF] Simplify dumping of a .debug_addr section.
This patch removes the part which tried to interpret addresses
in that section as offsets and simplifies the remaining code.
Differential Revision: https://reviews.llvm.org/D64020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364896
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Roman Lebedev [Tue, 2 Jul 2019 09:27:34 +0000 (09:27 +0000)]
[NFC][InstCombine] Add tests for "redundant shift input masking" (PR42456)
https://bugs.llvm.org/show_bug.cgi?id=42456
https://rise4fun.com/Alive/Vf1p
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364894
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Amara Emerson [Tue, 2 Jul 2019 06:04:46 +0000 (06:04 +0000)]
[TailDuplicator] Fix copy instruction emitting into the wrong block.
The code for duplicating instructions could sometimes try to emit copies
intended to deal with unconstrainable register classes to the tail block of the
original instruction, rather than before the newly cloned instruction in the
predecessor block.
This was exposed by GlobalISel on arm64.
Differential Revision: https://reviews.llvm.org/D64049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364888
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Craig Topper [Tue, 2 Jul 2019 05:53:37 +0000 (05:53 +0000)]
[X86] Add PreprocessISelDAG support for turning ISD::FP_TO_SINT/UINT into X86ISD::CVTTP2SI/CVTTP2UI and to reduce the number of isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364887
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QingShan Zhang [Tue, 2 Jul 2019 03:28:52 +0000 (03:28 +0000)]
[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook
After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise,
and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition
Differential Revision: https://reviews.llvm.org/D63804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364886
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Zi Xuan Wu [Tue, 2 Jul 2019 02:54:52 +0000 (02:54 +0000)]
[DAGCombiner] Exploiting more about the transformation of TransformFPLoadStorePair function
For a given floating point load / store pair, if the load value isn't used by any other operations,
then consider transforming the pair to integer load / store operations if the target deems the transformation profitable.
And we can exploiting much more when there are other operation nodes with chain operand between the load/store pair
so long as we keep the chain ordering original. We only replace the register used to load/store from float to integer.
I only add testcase in ARM because the TLI.isDesirableToTransformToIntegerOp hook is only enabled in ARM target.
Differential Revision: https://reviews.llvm.org/D60601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364883
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Jordan Rupprecht [Mon, 1 Jul 2019 23:29:46 +0000 (23:29 +0000)]
Revert Recommit [PowerPC] Update P9 vector costs for insert/extract element
This reverts r364557 (git commit
9f7f5858fe46b8e706e87a83e2fd0a2678be619e)
This crashes as reported on the commit thread. Repro instructions TBD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364876
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Keno Fischer [Mon, 1 Jul 2019 23:15:07 +0000 (23:15 +0000)]
[cmake] With utils disabled, don't build tblgen in cross mode
Summary:
In cross mode, we build a separate NATIVE tblgen that runs on the
host and is used during the build. Separately, we have a flag that
disables building all executables in utils/. Of course generally,
this doesn't turn off tblgen, since we need that during the build.
In cross mode, however, that tblegen is useless since we never
actually use it. Furthermore, it can be actively problematic if the
cross toolchain doesn't like building executables for whatever reason.
And even if building executables works fine, we can at least save
compile time by omitting it from the target build. There's two changes
needed to make this happen:
- Stop creating a dependency from the native tool to the target tool.
No such dependency is required for a correct build, so I'm not entirely
sure why it was there in the first place.
- If utils were disabled on the CMake command line and we're in cross mode,
respect that by excluding it from the install target (using EXCLUDE_FROM_ALL).
Reviewers: smeenai
Differential Revision: https://reviews.llvm.org/D64032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364872
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Reid Kleckner [Mon, 1 Jul 2019 22:43:39 +0000 (22:43 +0000)]
[PGO] Update ICP pass for recent byval type changes
Fixes verifier errors encountered in PR42413.
Reviewers: xur, t.p.northover, inglorion, gbiv, george.burgess.iv
Differential Revision: https://reviews.llvm.org/D63842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364861
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Matt Arsenault [Mon, 1 Jul 2019 22:01:05 +0000 (22:01 +0000)]
AMDGPU: Correct properties for adjcallstack* pseudos
These should be SALU writes, and these are lowered to instructions
that def SCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364859
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Matt Arsenault [Mon, 1 Jul 2019 22:00:59 +0000 (22:00 +0000)]
Fix broken C++ mode comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364858
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Huihui Zhang [Mon, 1 Jul 2019 22:00:32 +0000 (22:00 +0000)]
[InstCombine][NFCI] Update test cases in onehot_merge.ll
Use both one bit and signbit shifting to check for one bit merge.
Reviewers: lebedev.ri, spatel, efriedma, craig.topper
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364857
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Sanjay Patel [Mon, 1 Jul 2019 22:00:00 +0000 (22:00 +0000)]
[InstCombine] reduce more checks for power-of-2-or-zero using ctpop
Extends the transform from:
rL364341
...to include another (more common?) pattern that tests whether a
value is a power-of-2 (including or excluding zero).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364856
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Craig Topper [Mon, 1 Jul 2019 21:25:11 +0000 (21:25 +0000)]
[X86] Use v4i32 vzloads instead of v2i64 for vpmovzx/vpmovsx patterns where only 32-bits are loaded.
v2i64 vzload defines a 64-bit memory access. It doesn't look like
we have any coverage for this either way.
Also remove some vzload usages where the instruction loads only
16-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364851
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Simon Atanasyan [Mon, 1 Jul 2019 21:25:04 +0000 (21:25 +0000)]
[mips] Add missing schedinfo for MIPSeh_return[32|64] instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364850
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Simon Atanasyan [Mon, 1 Jul 2019 21:24:58 +0000 (21:24 +0000)]
[mips] Add virtualization ASE to P5600 scheduling definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364849
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Simon Atanasyan [Mon, 1 Jul 2019 21:24:51 +0000 (21:24 +0000)]
[mips] Add missing schedinfo for LONG_BRANCH_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364848
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Craig Topper [Mon, 1 Jul 2019 21:23:38 +0000 (21:23 +0000)]
[X86] Remove several bad load folding isel patterns for VPMOVZX/VPMOVSX.
These patterns all matched a v2i64 vzload which only loads 64-bits
to instructions that load a full 128-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364847
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Jordan Rupprecht [Mon, 1 Jul 2019 21:10:43 +0000 (21:10 +0000)]
Revert [SLP] Look-ahead operand reordering heuristic.
This reverts r364478 (git commit
574cb0eb3a7ac95e62d223a60bef891171dfe321)
The patch is causing compilation timeouts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364846
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Roman Lebedev [Mon, 1 Jul 2019 20:33:56 +0000 (20:33 +0000)]
[NFC][InstCombine] More commutative tests for "shift direction in bittest" (PR42466)
'and' is commutative, if we don't want to touch shift-of-const,
we still need to check the other hand of 'and'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364844
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Nilanjana Basu [Mon, 1 Jul 2019 20:27:37 +0000 (20:27 +0000)]
Testing commit access through minor formatting change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364843
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Matt Arsenault [Mon, 1 Jul 2019 19:36:10 +0000 (19:36 +0000)]
GlobalISel: Try to widen merges with other merges
If the requested source type an be used as a merge source type, create
a merge of merges. This avoids creating large, illegal extensions and
bit-ops directly to the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364841
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Matt Arsenault [Mon, 1 Jul 2019 19:09:57 +0000 (19:09 +0000)]
AMDGPU: Revert accidental change to test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364839
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Craig Topper [Mon, 1 Jul 2019 19:01:37 +0000 (19:01 +0000)]
[X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns
These instructions only read 64-bits of memory so we shouldn't
allow a full vector width load to be pattern matched in case it
is marked volatile.
Instead allow vzload or scalar_to_vector+load.
Also add a DAG combine to turn full vector loads into vzload when
used by one of these instructions if the load isn't volatile.
This fixes another case for PR42079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364838
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Matt Arsenault [Mon, 1 Jul 2019 18:50:50 +0000 (18:50 +0000)]
AMDGPU/GlobalISel: Handle more input argument intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364836
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Matt Arsenault [Mon, 1 Jul 2019 18:49:01 +0000 (18:49 +0000)]
AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364835
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Matt Arsenault [Mon, 1 Jul 2019 18:47:22 +0000 (18:47 +0000)]
AMDGPU/GlobalISel: Legalize workgroup ID intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364834
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Matt Arsenault [Mon, 1 Jul 2019 18:45:36 +0000 (18:45 +0000)]
AMDGPU/GlobalISel: Legalize workitem ID intrinsics
Tests don't cover the masked input path since non-kernel arguments
aren't lowered yet.
Test is copied directly from the existing test, with 2 additions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364833
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Matt Arsenault [Mon, 1 Jul 2019 18:40:23 +0000 (18:40 +0000)]
AMDGPU/GlobalISel: Custom lower control flow intrinsics
Replace the brcond for the 2 cases that act as branches. For now
follow how the current system works, although I think we can
eventually get rid of the pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364832
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Matt Arsenault [Mon, 1 Jul 2019 18:33:37 +0000 (18:33 +0000)]
AMDGPU/GlobalISel: Handle 16-bit SALU min/max
This needs to be extended to s32, and expanded into cmp+select. This
is relying on the fact that widenScalar happens to leave the
instruction in place, but this isn't a guaranteed property of
LegalizerHelper.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364831
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Matt Arsenault [Mon, 1 Jul 2019 18:30:45 +0000 (18:30 +0000)]
AMDGPU/GlobalISel: Lower SALU min/max to cmp+select
Use a change observer to apply a register bank to the newly created
intermediate result register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364830
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Robert Lougher [Mon, 1 Jul 2019 18:28:21 +0000 (18:28 +0000)]
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2)
The function findPotentialBlockers may consider debug info instructions as
potential blockers and may stop searching for a store-load pair prematurely.
This patch corrects this and tests the cases where the store is separated
from the load by more than InspectionLimit debug instructions.
Patch by Chris Dawson.
Differential Revision: https://reviews.llvm.org/D62408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364829
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Matt Arsenault [Mon, 1 Jul 2019 18:26:47 +0000 (18:26 +0000)]
AMDGPU/GlobalISel: Add tests for add legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364828
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Matt Arsenault [Mon, 1 Jul 2019 18:18:55 +0000 (18:18 +0000)]
AMDGPU/GlobalISel: Legalize s16 add/sub/mul
If this is scalar, promote to s32. Use a new observer class to assign
the register bank of newly created registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364827
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Matt Arsenault [Mon, 1 Jul 2019 18:13:12 +0000 (18:13 +0000)]
AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECT
The condition register bank must be scc or vcc so that a copy will be
inserted, which will be lowered to a compare.
Currently greedy unnecessarily forces using a VCC select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364825
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Roman Lebedev [Mon, 1 Jul 2019 18:11:32 +0000 (18:11 +0000)]
[NFC][InstCombine] Add tests for "shift direction in bittest" (PR42466)
https://rise4fun.com/Alive/8O1
https://bugs.llvm.org/show_bug.cgi?id=42466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364824
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Matt Arsenault [Mon, 1 Jul 2019 18:01:35 +0000 (18:01 +0000)]
GlobalISel: Verify G_MERGE_VALUES operand sizes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364822
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Aditya Nandakumar [Mon, 1 Jul 2019 17:53:50 +0000 (17:53 +0000)]
[GlobalISel]: Allow backends to custom legalize Intrinsics
https://reviews.llvm.org/D31359
Add a hook "legalizeInstrinsic" to allow backends to override this
and custom lower/legalize intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364821
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Matt Arsenault [Mon, 1 Jul 2019 17:40:18 +0000 (17:40 +0000)]
AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364819
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Matt Arsenault [Mon, 1 Jul 2019 17:35:53 +0000 (17:35 +0000)]
AMDGPU/GlobalISel: Legalize s16 fcmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364817
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Matt Arsenault [Mon, 1 Jul 2019 17:18:03 +0000 (17:18 +0000)]
GlobalISel: Implement lower for min/max
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364816
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Nicolai Haehnle [Mon, 1 Jul 2019 17:17:52 +0000 (17:17 +0000)]
AMDGPU/GFX10: implement ds_ordered_count changes
Summary:
ds_ordered_count can now simultaneously operate on up to 4 dwords
in a single instruction, which are taken from (and returned to)
lanes 0..3 of a single VGPR.
Change-Id: I19b6e7b0732b617c10a779a7f9c0303eec7dd276
Reviewers: mareko, arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364815
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Nicolai Haehnle [Mon, 1 Jul 2019 17:17:45 +0000 (17:17 +0000)]
AMDGPU: Support GDS atomics
Summary:
Original patch by Marek Olšák
Change-Id: Ia97d5d685a63a377d86e82942436d1fe6e429bab
Reviewers: mareko, arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, jfb, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364814
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Matt Arsenault [Mon, 1 Jul 2019 17:04:57 +0000 (17:04 +0000)]
AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364811
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Matt Arsenault [Mon, 1 Jul 2019 17:02:24 +0000 (17:02 +0000)]
AArch64/GlobalISel: Fix trying to select invalid MIR
Physical registers are not allowed to be a phi operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364810
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Matt Arsenault [Mon, 1 Jul 2019 16:41:36 +0000 (16:41 +0000)]
AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelane
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364808
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Matt Arsenault [Mon, 1 Jul 2019 16:36:39 +0000 (16:36 +0000)]
AMDGPU/GlobalISel: Fail instead of assert when selecting loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364807
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Matt Arsenault [Mon, 1 Jul 2019 16:34:48 +0000 (16:34 +0000)]
AMDGPU/GlobalISel: Complete implementation of G_GEP
Also works around tablegen defect in selecting add with unused carry,
but if we have to manually select GEP, might as well handle add
manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364806
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Matt Arsenault [Mon, 1 Jul 2019 16:32:47 +0000 (16:32 +0000)]
AMDGPU/GlobalISel: Select G_PHI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364805
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Matt Arsenault [Mon, 1 Jul 2019 16:27:32 +0000 (16:27 +0000)]
AMDGPU/GlobalISel: Try to select VOP3 form of add
There are several things broken, but at least emit the right thing for
gfx9.
The import of the pattern with the unused carry out seems to not
work. Needs a special class for clamp, because OperandWithDefaultOps
doesn't really work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364804
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Simon Pilgrim [Mon, 1 Jul 2019 16:20:47 +0000 (16:20 +0000)]
[X86] Add widenSubVector to size in bits helper. NFCI.
We can already widenSubVector to a specific type (of the same scalar type) - this variant just specifies the target vector size.
This will be useful when CombineShuffleWithExtract relaxes the need to have the same scalar type for all shuffle operand subvector sources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364803
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Matt Arsenault [Mon, 1 Jul 2019 16:19:39 +0000 (16:19 +0000)]
AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364801
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James Henderson [Mon, 1 Jul 2019 16:18:57 +0000 (16:18 +0000)]
[docs][llvm-readelf] Expand llvm-readelf documentation
Previously, the llvm-readelf documentation was essentially just a list
of differences to llvm-readobj. Since llvm-readelf is the more likely
goto tool for many people migrating to the LLVM toolchain, it seems like
it would be helpful to document all the switches in the llvm-readelf
document too. This change expands the options listed accordingly.
Additionally, they are unlikely to care what the differences are to
llvm-readobj, since they won't be familiar with the latter as there is
no GNU equivalent, so this change moves the "differences" section to
llvm-readobj's documentation.
Reviewed by: peter.smith
Differential Revision: https://reviews.llvm.org/D63826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364800
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Tom Stellard [Mon, 1 Jul 2019 16:09:33 +0000 (16:09 +0000)]
AMDGPU/GlobalISel: Implement select for 32-bit G_ADD
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364797
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Mikhail Maltsev [Mon, 1 Jul 2019 16:07:58 +0000 (16:07 +0000)]
[ARM] Fix MVE_VQxDMLxDH instruction class
Summary:
According to the ARMARM, the VQDMLADH, VQRDMLADH, VQDMLSDH and
VQRDMLSDH instructions handle their results as follows: "The base
variant writes the results into the lower element of each pair of
elements in the destination register, whereas the exchange variant
writes to the upper element in each pair". I.e., the initial content
of the output register affects the result, as usual, we model this
with an additional input.
Also, for 32-bit variants Qd is not allowed to be the same register as
Qm and Qn, we use @earlyclobber to indicate this.
This patch also changes vpred_r to vpred_n because the instructions
don't have an explicit 'inactive' operand.
Reviewers: dmgreen, ostannard, simon_tatham
Reviewed By: simon_tatham
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364796
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Matt Arsenault [Mon, 1 Jul 2019 16:06:02 +0000 (16:06 +0000)]
AMDGPU/GlobalISel: Select G_BRCOND for vcc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364795
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Mikhail Maltsev [Mon, 1 Jul 2019 16:05:23 +0000 (16:05 +0000)]
[ARM] MVE: support QQPRRegClass and QQQQPRRegClass
Summary:
QQPRRegClass and QQQQPRRegClass are used by the
interleaving/deinterleaving loads/stores to represent sequences of
consecutive SIMD registers.
Reviewers: ostannard, simon_tatham, dmgreen
Reviewed By: simon_tatham
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364794
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Krzysztof Parzyszek [Mon, 1 Jul 2019 16:01:15 +0000 (16:01 +0000)]
Update email address in CODE_OWNERS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364793
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Roman Lebedev [Mon, 1 Jul 2019 15:55:24 +0000 (15:55 +0000)]
[InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459)
Summary:
To be noted, this pattern is not unhandled by instcombine per-se,
it is somehow does end up being folded when one runs opt -O3,
but not if it's just -instcombine. Regardless, that fold is
indirect, depends on some other folds, and is thus blind
when there are extra uses.
This does address the regression being exposed in D63992.
https://godbolt.org/z/7DGltU
https://rise4fun.com/Alive/EPO0
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42459 | PR42459 ]]
Reviewers: spatel, nikic, huihuiz
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364792
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Roman Lebedev [Mon, 1 Jul 2019 15:55:15 +0000 (15:55 +0000)]
[InstCombine] Shift amount reassociation in bittest (PR42399)
Summary:
Given pattern:
`icmp eq/ne (and ((x shift Q), (y oppositeshift K))), 0`
we should move shifts to the same hand of 'and', i.e. rewrite as
`icmp eq/ne (and (x shift (Q+K)), y), 0` iff `(Q+K) u< bitwidth(x)`
It might be tempting to not restrict this to situations where we know
we'd fold two shifts together, but i'm not sure what rules should there be
to avoid endless combine loops.
We pick the same shift that was originally used to shift the variable we picked to shift:
https://rise4fun.com/Alive/6x1v
Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42399 | PR42399]].
Reviewers: spatel, nikic, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364791
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Krzysztof Parzyszek [Mon, 1 Jul 2019 15:50:09 +0000 (15:50 +0000)]
[Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364790
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Matt Arsenault [Mon, 1 Jul 2019 15:48:18 +0000 (15:48 +0000)]
AMDGPU/GlobalISel: Select G_FRAME_INDEX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364789
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Nicolai Haehnle [Mon, 1 Jul 2019 15:43:00 +0000 (15:43 +0000)]
AMDGPU/GFX10: fix scratch resource descriptor
Summary:
The stride should depend on the wave size, not the hardware generation.
Also, the 32_FLOAT format is 0x16, not 16; though that shouldn't be
relevant.
Change-Id: I088f93bf6708974d085d1c50967f119061da6dc6
Reviewers: arsenm, rampitec, mareko
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364788
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Matt Arsenault [Mon, 1 Jul 2019 15:42:47 +0000 (15:42 +0000)]
AMDGPU/GlobalISel: Make s16 select legal
This is easy to handle and avoids legalization artifacts which are
likely to obscure combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364787
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Matt Arsenault [Mon, 1 Jul 2019 15:39:27 +0000 (15:39 +0000)]
AMDGPU/GlobalISel: Select G_BRCOND for scc conditions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364786
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Matt Arsenault [Mon, 1 Jul 2019 15:23:04 +0000 (15:23 +0000)]
AMDGPU/GlobalISel: Tolerate copies with no type set
isVCC has the same bug, but isn't used in a context where it can cause
a problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364784
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Matt Arsenault [Mon, 1 Jul 2019 15:23:03 +0000 (15:23 +0000)]
AMDGPU: Fix tests using the default alloca address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364783
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Matt Arsenault [Mon, 1 Jul 2019 15:18:56 +0000 (15:18 +0000)]
AMDGPU/GlobalISel: Select src modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364782
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Diana Picus [Mon, 1 Jul 2019 15:07:38 +0000 (15:07 +0000)]
Fixup r364512
Fix stack-use-after-scope errors from r364512. One instance was already
fixed in r364611 - this patch simplifies that fix and addresses one more
instance of similar code.
Discussed in: https://reviews.llvm.org/D63905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364778
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Jinsong Ji [Mon, 1 Jul 2019 14:37:48 +0000 (14:37 +0000)]
[UpdateTestChecks][PowerPC] Avoid empty string when scrubbing loop comments
Summary:
SCRUB_LOOP_COMMENT_RE was introduced in https://reviews.llvm.org/D31285
This works for some loops.
However, we may generate lines with loop comments only.
And since we don't scrub leading white spaces, this will leave an empty
line there, and FileCheck will complain it.
eg: llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll:27:15:
error: found empty check string with prefix 'CHECK:'
; CHECK-NEXT:
This prevented us from using the `update_llc_test_checks.py` for quite some cases.
We should still keep the comment token there, so that we can safely
scrub the loop comment without breaking FileCheck.
Reviewers: timshen, hfinkel, lebedev.ri, RKSimon
Subscribers: nemanjai, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364775
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Roman Lebedev [Mon, 1 Jul 2019 14:28:24 +0000 (14:28 +0000)]
[NFC][InstCombine] Better commutative tests for "shift amount reassociation in bittest" pattern.
As discussed in https://reviews.llvm.org/D63829
*if* *both* shifts are one-use, we'd most likely want to produce `lshr`,
and not rely on ordering.
Also, there should likely be a *separate* fold to do this reordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364772
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Krzysztof Parzyszek [Mon, 1 Jul 2019 13:50:47 +0000 (13:50 +0000)]
[Hexagon] Rework VLCR algorithm
Add code to catch pattern for commutative instructions for VLCR.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364770
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Matt Arsenault [Mon, 1 Jul 2019 13:44:46 +0000 (13:44 +0000)]
AMDGPU: Convert some places to Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364769
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Matt Arsenault [Mon, 1 Jul 2019 13:40:18 +0000 (13:40 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364768
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Matt Arsenault [Mon, 1 Jul 2019 13:40:17 +0000 (13:40 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364767
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Matt Arsenault [Mon, 1 Jul 2019 13:37:39 +0000 (13:37 +0000)]
AMDGPU/GlobalISel: Fail on store to 32-bit address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364766
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