Ivan Grokhotkov [Fri, 13 Jan 2017 03:51:40 +0000 (11:51 +0800)]
Merge branch 'feature/esp32_core_dump' into 'master'
esp32 core dump to flash
1. menuconfig option to select where to store core dump: flash, uart or disable
2. Saving of core dump to flash
3. Partition table definitions files with core dump partition
4. Python scripts to support core dump generation from GDB command line
Alexey Gerenkov [Tue, 10 Jan 2017 11:48:47 +0000 (14:48 +0300)]
esp32: Fixes issues discussed during code review of MR!341
The following issues mentioned during MR!341 review were fixed:
1) Core dump test application description
2) Usage of CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH and CONFIG_ESP32_ENABLE_COREDUMP_TO_UART
3) FLASH_GUARD_START macro usage is fixed in flash API
4) Core dump module logging facility
5) cache util functions doc updated
6) interactive delay before print core dump to uart
7) core dump partion support in build system
Ivan Grokhotkov [Thu, 12 Jan 2017 07:53:09 +0000 (15:53 +0800)]
Merge branch 'bugfix/deep_sleep' into 'master'
deep sleep related fixes
A few fixes for deep sleep behavior:
- Fix a regression that deep sleep stub crashed if `ESP32_DEEP_SLEEP_WAKEUP_DELAY` option was enabled — the stub called `ets_update_cpu_frequency`, which was recently redefined to be an IRAM function, rather than a ROM one. Fixed by restoring the ROM definition as `ets_update_cpu_frequency_rom`, and using that in the deep sleep stub.
- By default, don't power down RTC_SLOW_MEM if there is any data in .rtc.data or .rtc.bss sections. This provides better out-of-the box experience, as variables attributed to .rtc.data are actually preserved during deep sleep.
- Store boot time in RTC_STORE registers instead of using a variable with RTC_DATA_ATTR. This allows RTC_SLOW_MEM to be powered down in deep sleep if no variables with RTC_DATA_ATTR are present in the program.
Ivan Grokhotkov [Wed, 11 Jan 2017 09:17:13 +0000 (17:17 +0800)]
deep sleep: fix regression due to moving ets_update_cpu_frequency into IRAM
Deep sleep stub may call ets_update_cpu_frequency, which has been moved from ROM to IRAM.
Restore the ROM version in the linker script, call it ets_update_cpu_frequency_rom, use it in the deep sleep stub.
Ivan Grokhotkov [Thu, 12 Jan 2017 01:47:15 +0000 (09:47 +0800)]
Merge branch 'bugfix/mbedtls_tests' into 'master'
fix mbedtls unit tests, fix IDF_VER when building a project outside ESP-IDF tree
- mbedTLS test needs about 5% more time to run (in debug mode) when building with 5.2.0, compared to 4.8.5. Increase the timeout to let the test pass.
- when doing `git describe` in IDF_VER definition, `-C $(IDF_PATH)` is needed to get the version of ESP-IDF, and not the project being built (which may not even be in git)
Alexey Gerenkov [Tue, 3 Jan 2017 19:01:40 +0000 (22:01 +0300)]
esp32: Fixes several issues in core dump feature
1) PS is fixed up to allow GDB backtrace to work properly
2) MR!341 discussion: in core dump module: esp_panicPutXXX was replaced by ets_printf.
3) MR!341 discussion: core dump flash magic number was changed.
4) MR!341 discussion: SPI flash access API was redesigned to allow flexible critical section management.
5) test app for core dump feature was added
6) fixed base64 file reading issues on Windows platform
7) now raw bin core file is deleted upon core loader failure by epscoredump.py
Alexey Gerenkov [Wed, 21 Dec 2016 23:56:23 +0000 (02:56 +0300)]
esp32: Add core dump saving to flash feature
Complimentary changes:
1) Partition table definitions files with core dump partition
2) Special sub-type for core dump partition
3) Special version of spi_flash_xxx
4) espcoredump.py is script to get core dump from flash and print useful info
5) FreeRTOS API was extended to get tasks snapshots
Ivan Grokhotkov [Wed, 11 Jan 2017 10:38:30 +0000 (18:38 +0800)]
Merge branch 'feature/config_wifi_bt' into 'master'
Clean up WiFi & Bluetooth config options
* Splits "WiFi" configuration out from ESP32 configuration submenu to its own menu.
* Renames "BT" to "Bluetooth", enabling Bluetooth is now in this option not the ESP32 submenu.
* Also disables compiling/linking of BT stack if Bluetooth is disabled, saves some build time.
Ivan Grokhotkov [Wed, 11 Jan 2017 10:37:45 +0000 (18:37 +0800)]
Merge branch 'feature/toolchain_update' into 'master'
update toolchain version, rebuild newlib
- This MR updates the toolchain version used in the ESP-IDF
- Compiler version check and warning is added to project.mk
- Newlib is rebuilt to include wcsftime function
- libstdc++ build uses correct newlib headers (so we won't get undefined reference to `__impure_ptr` anymore)
Jeroen Domburg [Wed, 11 Jan 2017 09:11:45 +0000 (17:11 +0800)]
Merge branch 'bugfix/spi_inconsistencies' into 'master'
SPI: Some fixes to docs and flag naming
Kolban noticed the flags for a transaction are not named like the documentation states. The flags as mentioned in the docs are more consistent, so this MR renames them to that. Also some additions to the docs wrt the SPI signals
Ref http://www.esp32.com/viewtopic.php?f=13&t=919&p=3976#p3976 and http://www.esp32.com/viewtopic.php?f=13&t=921&p=3975#p3975
Merge branch 'bugfix/id9561_bt_status_check' into 'master'
component/bt: bug fix of lack of checking bluetooth stack status inside API functions
Add an API function for checking bluetooth stack status: whether it is uninitialized, initialized or enabled.
The function is intended to be used by users to check the bluetooth stack status, also, it is used inside bluetooth API functions to ensure the stack is in valid state.
Ivan Grokhotkov [Wed, 11 Jan 2017 04:07:43 +0000 (12:07 +0800)]
Merge branch 'bugfix/crosscore_int_iram' into 'master'
Place cross-core interrupt into IRAM, sanity check handler address passed into esp_intr_alloc
Cross-core interrupt handler was not marked with IRAM_ATTR.
The reason why this caused an exception is probably due to some tasks running at highest priority (these are not blocked by spi_flash_disable_caches_interrupts_and_other_cpu mechanism).
This change puts the interrupt handler into IRAM and adds a sanity check into `esp_intr_alloc`.
Reported on Github: https://github.com/espressif/esp-idf/issues/211
Jeroen Domburg [Tue, 10 Jan 2017 06:41:12 +0000 (14:41 +0800)]
SPI master: rename transaction flags from SPI_* to SPI_TRANS_*, like the documentation says. Also add some explanation about the SPI signals in the documentation
Jeroen Domburg [Tue, 10 Jan 2017 06:01:07 +0000 (14:01 +0800)]
Merge branch 'feature/watchpoint_on_stack_canary' into 'master'
Add option to automatically set a watchpoint at the end of the swapped-in task
This should make stack overflows easier to debug because it triggers a debug exception as soon as the stack is overwritten, not later when a context switch happens. Marked as a FreeRTOS debug feature because it doesn't give a nice error message and uses up a watchpoint.
Jeroen Domburg [Tue, 10 Jan 2017 05:05:19 +0000 (13:05 +0800)]
Add documentation to panic handler functions, move watchpoint stuff from tasks.c to port.c, account for non-32-bytes-aligned stacks when setting watchpoint, add debug reason explanation to panic handler
Merge branch 'bugfix/detect_ocd_when_panic' into 'master'
Fix OpenOCD detection code
In the current master, detection of an attached OCD is broken. This fixes it.
I also snuck in two unrelated checks in intr_alloc which return from a function that is asserted earlier in the code. This makes the code behave better when they are called erroneously in a production build.
Ivan Grokhotkov [Mon, 9 Jan 2017 02:14:00 +0000 (10:14 +0800)]
Merge branch 'bugfix/bootloader_ets_cpu_update_freq' into 'master'
bootloader: export ets_update_cpu_frequency
MR !363 added linking librtc into bootloader. At the same time, MR !373 removed ets_update_cpu_frequency from ROM exports ld script, and replaced it with a dual CPU aware version. Combining these two MRs caused linker error in bootloader due to the unresolved `ets_update_cpu_frequency`.
One option to fix this is to move the definition of ets_update_cpu_frequency into bootloader_support component. This does however look a bit odd because this function is not something that is specifically needed for bootloader support.
Another option is to export the ROM version of ets_update_cpu_frequency for the bootloader only. This means that when bootloader changes CPU frequency, it only updates the tick period variable for PRO CPU. This isn't an issue though, because app startup code still calls the dual CPU aware version of ets_update_cpu_frequency early on, before any non-trivial code can run on the APP cpu.
This MR uses the second approach. Looking forward, we may move this definition of ets_update_cpu_frequency into the rtc_clk component, which will be used both by the bootloader and the app, and placing ets_update_cpu_frequency there would be logical.
This MR contains:
- SDMMC host peripheral driver
- SD protocol driver in sdmmc component (can be extended to support MMC/eMMC and SPI based hosts)
- ChaN's FATFS library v0.12b
- VFS integration
- FAT access via VFS is thread-safe (unless same file is read/written/unlinked/renamed from different tasks)
- Support for POSIX directory-related functions in VFS (and in vfs_fatfs.c)
- unit test for the above
- Example
- API documentation
Will be done in other MRs:
- Support for spi_flash IO driver for FatFs
- SPI host driver and support for SPI mode commands in sdmmc component
- MMC/eMMC support in sdmmc component
- Support for slightly higher 53/26.6MHz clocks (currently I'm using 20MHz for DS and 40MHz for HS, instead of 25MHz/50MHz per standard), and arbitrary low clocks (e.g. 4MHz).
Ivan Grokhotkov [Sat, 7 Jan 2017 10:50:12 +0000 (18:50 +0800)]
Merge branch 'feature/cplusplus' into 'master'
C++ support
This change adds necessary support for compiling C++ programs:
- linking against libstdc++
- implementation of static initialization guards using FreeRTOS primitives: since we don't have condition variables at our disposal, and we don't want to allocate a synchronization primitive for every guard variable generated by the compiler, we imitate condition variables using a combination of a mutex, counting semaphore, and a counter (based on [Microsoft Research paper](https://www.microsoft.com/en-us/research/wp-content/uploads/2004/12/ImplementingCVs.pdf), albeit because we don't need *arbitrary* code to use these CVs, implementation gets simpler).
Note that libstdc++ also contains an implementation of `__cxa_guard_{acquire,release,abort}` functions. These implementations come from an `#ifndef GXX_THREADS` branch, i.e. are not aware of multthreading. There are three ways of replacing these libstdc++ functions with our implementation:
1. Move our code into gcc. Pros: cleanest solution. Cons: Such changes are unlikely to be merged by any upstream, so we end up maintaining our own forks of {gcc,crosstool-ng}.
2. Use library as it is built by crosstool, use `ar` to delete one object file (`guards.o`), add this library to ESP-IDF. Pros: easy to implement. Cons: libstdc++ is a 15MB binary :hushed:
3. Keep using libstdc++ from crosstool, force our implementation to be linked using a `-u` linker flag. Pros: no impact on repo size, easy to implement. Cons: somewhat less clean than 1 (and about as hacky as 2).
For the reasons mentioned, option (3) looks like the best tradeoff.
Ivan Grokhotkov [Sat, 7 Jan 2017 10:46:10 +0000 (18:46 +0800)]
Merge branch 'feature/bootloader_rng' into 'master'
Enable bootloader entropy source for RNG
Enables an entropy source when bootloader starts up, which both seeds the RNG for use before WiFi/BT stack is enabled and provides an adequate RNG for secure boot & flash encryption key generation.
A prerequisite was enabling 80MHz operation, so the CPU is now set to 80MHz as soon as second stage bootloader starts running.
Ivan Grokhotkov [Sat, 7 Jan 2017 10:45:14 +0000 (18:45 +0800)]
Merge branch 'bugfix/ets_delay_on_app_cpu' into 'master'
esp32: ets_update_cpu_frequency should set tick scale for both CPUs
ets_update_cpu_frequency ROM function updates g_ticks_per_us, which is has two copies, one for each CPU.
The APP CPU copy of g_ticks_per_us never got updated, resulting in shorter delays produced by ets_delay_us on the APP CPU.
This MR replaces ROM ets_update_cpu_frequency with a copy in IRAM which updates scaling factors on both of the CPUs.
So now we get expected delays (in microseconds):
```
ets_delay_us core=0 expected=50000 actual=50014
ets_delay_us core=1 expected=50000 actual=50015
vTaskDelay core=0 expected=50000 actual=49428
vTaskDelay core=1 expected=50000 actual=50000
```
Reported on the forum: http://esp32.com/viewtopic.php?f=2&t=713#p3722