Joerg Sonnenberger [Thu, 29 Aug 2019 13:22:30 +0000 (13:22 +0000)]
Allow replaceAndRecursivelySimplify to list unsimplified visitees.
This is part of D65280 and split it to avoid ABI changes on the 9.0
release branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370355
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Thu, 29 Aug 2019 13:19:50 +0000 (13:19 +0000)]
[mips] Inline emitStoreWithSymOffset and emitLoadWithSymOffset methods. NFC
Both methods `MipsTargetStreamer::emitStoreWithSymOffset` and
`MipsTargetStreamer::emitLoadWithSymOffset` are almost the same and
differ argument names only. These methods are used in the single place
so it's better to inline their code and remove original methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370354
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Thu, 29 Aug 2019 13:19:38 +0000 (13:19 +0000)]
[mips] Fix expanding `lw/sw $reg1, symbol($reg2)` instruction
When a "base" in the `lw/sw $reg1, symbol($reg2)` instruction is
a register and generated code is position independent, backend
does not add the "base" value to the symbol address.
```
lw $reg1, %got(symbol)($gp)
lw/sw $reg1, 0($reg1)
```
This patch fixes the bug and adds the missed `addu` instruction by
passing `BaseReg` into the `loadAndAddSymbolAddress` routine and handles
the case when the `BaseReg` is the zero register to escape redundant
`move reg, reg` instruction:
```
lw $reg1, %got(symbol)($gp)
addu $reg1, $reg1, $reg2
lw/sw $reg1, 0($reg1)
```
Differential Revision: https://reviews.llvm.org/D66894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370353
91177308-0d34-0410-b5e6-
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Roman Lebedev [Thu, 29 Aug 2019 12:48:04 +0000 (12:48 +0000)]
[InstSimplify] Drop leftover "division-by-zero guard" around `@llvm.umul.with.overflow` inverted overflow bit
Summary:
Now that with D65143/D65144 we've produce `@llvm.umul.with.overflow`,
and with D65147 we've flattened the CFG, we now can see that
the guard may have been there to prevent division by zero is redundant.
We can simply drop it:
```
----------------------------------------
Name: no overflow or zero
%iszero = icmp eq i4 %y, 0
%umul = smul_overflow i4 %x, %y
%umul.ov = extractvalue {i4, i1} %umul, 1
%umul.ov.not = xor %umul.ov, -1
%retval.0 = or i1 %iszero, %umul.ov.not
ret i1 %retval.0
=>
%iszero = icmp eq i4 %y, 0
%umul = smul_overflow i4 %x, %y
%umul.ov = extractvalue {i4, i1} %umul, 1
%umul.ov.not = xor %umul.ov, -1
%retval.0 = or i1 %iszero, %umul.ov.not
ret i1 %umul.ov.not
Done: 1
Optimization is correct!
```
Note that this is inverted from what we have in a previous patch,
here we are looking for the inverted overflow bit.
And that inversion is kinda problematic - given this particular
pattern we neither hoist that `not` closer to `ret` (then the pattern
would have been identical to the one without inversion,
and would have been handled by the previous patch), neither
do the opposite transform. But regardless, we should handle this too.
I've filled [[ https://bugs.llvm.org/show_bug.cgi?id=42720 | PR42720 ]].
Reviewers: nikic, spatel, xbolva00, RKSimon
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370351
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Thu, 29 Aug 2019 12:47:50 +0000 (12:47 +0000)]
[InstSimplify] Drop leftover "division-by-zero guard" around `@llvm.umul.with.overflow` overflow bit
Summary:
Now that with D65143/D65144 we've produce `@llvm.umul.with.overflow`,
and with D65147 we've flattened the CFG, we now can see that
the guard may have been there to prevent division by zero is redundant.
We can simply drop it:
```
----------------------------------------
Name: no overflow and not zero
%iszero = icmp ne i4 %y, 0
%umul = umul_overflow i4 %x, %y
%umul.ov = extractvalue {i4, i1} %umul, 1
%retval.0 = and i1 %iszero, %umul.ov
ret i1 %retval.0
=>
%iszero = icmp ne i4 %y, 0
%umul = umul_overflow i4 %x, %y
%umul.ov = extractvalue {i4, i1} %umul, 1
%retval.0 = and i1 %iszero, %umul.ov
ret %umul.ov
Done: 1
Optimization is correct!
```
Reviewers: nikic, spatel, xbolva00
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370350
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Roman Lebedev [Thu, 29 Aug 2019 12:47:34 +0000 (12:47 +0000)]
[SimplifyCFG] FoldTwoEntryPHINode(): don't bailout on i1 PHI's if we can hoist a 'not' from incoming values
Summary:
As it can be seen in the tests in D65143/D65144, even though we have formed an '@llvm.umul.with.overflow'
and got rid of potential for division-by-zero, the control flow remains, we still have that branch.
We have this condition:
```
// Don't fold i1 branches on PHIs which contain binary operators
// These can often be turned into switches and other things.
if (PN->getType()->isIntegerTy(1) &&
(isa<BinaryOperator>(PN->getIncomingValue(0)) ||
isa<BinaryOperator>(PN->getIncomingValue(1)) ||
isa<BinaryOperator>(IfCond)))
return false;
```
which was added back in rL121764 to help with `select` formation i think?
That check prevents us to flatten the CFG here, even though we know
we no longer need that guard and will be able to drop everything
but the '@llvm.umul.with.overflow' + `not`.
As it can be seen from tests, we end here because the `not` is being
sinked into the PHI's incoming values by InstCombine,
so we can't workaround this by hoisting it to after PHI.
Thus i suggest that we relax that check to not bailout if we'd get to hoist the `not`.
Reviewers: craig.topper, spatel, fhahn, nikic
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370349
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Roman Lebedev [Thu, 29 Aug 2019 12:47:20 +0000 (12:47 +0000)]
[InstCombine] Fold '((%x * %y) u/ %x) != %y' to '@llvm.umul.with.overflow' + overflow bit extraction
Summary:
`((%x * %y) u/ %x) != %y` is one of (3?) common ways to check that
some unsigned multiplication (will not) overflow.
Currently, we don't catch it. We could:
```
$ /repositories/alive2/build-Clang-unknown/alive -root-only ~/llvm-patch1.ll
Processing /home/lebedevri/llvm-patch1.ll..
----------------------------------------
Name: no overflow
%o0 = mul i4 %y, %x
%o1 = udiv i4 %o0, %x
%r = icmp ne i4 %o1, %y
ret i1 %r
=>
%n0 = umul_overflow i4 %x, %y
%o0 = extractvalue {i4, i1} %n0, 0
%o1 = udiv %o0, %x
%r = extractvalue {i4, i1} %n0, 1
ret %r
Done: 1
Optimization is correct!
----------------------------------------
Name: no overflow
%o0 = mul i4 %y, %x
%o1 = udiv i4 %o0, %x
%r = icmp eq i4 %o1, %y
ret i1 %r
=>
%n0 = umul_overflow i4 %x, %y
%o0 = extractvalue {i4, i1} %n0, 0
%o1 = udiv %o0, %x
%n1 = extractvalue {i4, i1} %n0, 1
%r = xor %n1, -1
ret i1 %r
Done: 1
Optimization is correct!
```
Reviewers: nikic, spatel, efriedma, xbolva00, RKSimon
Reviewed By: nikic
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370348
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Roman Lebedev [Thu, 29 Aug 2019 12:47:08 +0000 (12:47 +0000)]
[InstCombine] Fold '(-1 u/ %x) u< %y' to '@llvm.umul.with.overflow' + overflow bit extraction
Summary:
`(-1 u/ %x) u< %y` is one of (3?) common ways to check that
some unsigned multiplication (will not) overflow.
Currently, we don't catch it. We could:
```
----------------------------------------
Name: no overflow
%o0 = udiv i4 -1, %x
%r = icmp ult i4 %o0, %y
=>
%o0 = udiv i4 -1, %x
%n0 = umul_overflow i4 %x, %y
%r = extractvalue {i4, i1} %n0, 1
Done: 1
Optimization is correct!
----------------------------------------
Name: no overflow, swapped
%o0 = udiv i4 -1, %x
%r = icmp ugt i4 %y, %o0
=>
%o0 = udiv i4 -1, %x
%n0 = umul_overflow i4 %x, %y
%r = extractvalue {i4, i1} %n0, 1
Done: 1
Optimization is correct!
----------------------------------------
Name: overflow
%o0 = udiv i4 -1, %x
%r = icmp uge i4 %o0, %y
=>
%o0 = udiv i4 -1, %x
%n0 = umul_overflow i4 %x, %y
%n1 = extractvalue {i4, i1} %n0, 1
%r = xor %n1, -1
Done: 1
Optimization is correct!
----------------------------------------
Name: overflow
%o0 = udiv i4 -1, %x
%r = icmp ule i4 %y, %o0
=>
%o0 = udiv i4 -1, %x
%n0 = umul_overflow i4 %x, %y
%n1 = extractvalue {i4, i1} %n0, 1
%r = xor %n1, -1
Done: 1
Optimization is correct!
```
As it can be observed from tests, while simply forming the `@llvm.umul.with.overflow`
is easy, if we were looking for the inverted answer, then more work needs to be done
to cleanup the now-pointless control-flow that was guarding against division-by-zero.
This is being addressed in follow-up patches.
Reviewers: nikic, spatel, efriedma, xbolva00, RKSimon
Reviewed By: nikic, xbolva00
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370347
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Roman Lebedev [Thu, 29 Aug 2019 11:50:30 +0000 (11:50 +0000)]
[CostModel] Model all `extractvalue`s as free.
Summary:
As disscussed in https://reviews.llvm.org/D65148#
1606412,
`extractvalue` don't actually generate any code,
so we should treat them as free.
Reviewers: craig.topper, RKSimon, jnspaulsson, greened, asb, t.p.northover, jmolloy, dmgreen
Reviewed By: jmolloy
Subscribers: javed.absar, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370339
91177308-0d34-0410-b5e6-
96231b3b80d8
Jeremy Morse [Thu, 29 Aug 2019 11:20:54 +0000 (11:20 +0000)]
[DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locations
The missing line added by this patch ensures that only spilt variable
locations are candidates for being restored from the stack. Otherwise,
register or constant-value information can be interpreted as a spill
location, through a union.
The added regression test replicates a scenario where this occurs: the
stack load from [rsp] causes the register-location DBG_VALUE to be
"restored" to rsi, when it should be left alone. See PR43058 for details.
Un x-fail a test that was suffering from this from a previous patch.
Differential Revision: https://reviews.llvm.org/D66895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370334
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 29 Aug 2019 11:18:53 +0000 (11:18 +0000)]
Fix signed/unsigned comparison warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370333
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 29 Aug 2019 11:16:32 +0000 (11:16 +0000)]
Fix shadow variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370332
91177308-0d34-0410-b5e6-
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George Rimar [Thu, 29 Aug 2019 10:58:47 +0000 (10:58 +0000)]
[yaml2obj] - Allow placing local symbols after globals.
This allows us to produce broken binaries with local
symbols placed after global in '.dynsym'/'.symtab'
Also, simplifies the code.
Differential revision: https://reviews.llvm.org/D66799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370331
91177308-0d34-0410-b5e6-
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George Rimar [Thu, 29 Aug 2019 10:55:57 +0000 (10:55 +0000)]
[llvm-readobj/llvm-readelf] - Report a proper warning when dumping a broken dynamic relocation.
When we have a dynamic relocation with a broken symbol's st_name,
tools report a useless error: "Invalid data was encountered while parsing the file".
After this change we report a warning + "<corrupt>" as a symbol name.
Differential revision: https://reviews.llvm.org/D66734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370330
91177308-0d34-0410-b5e6-
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David Green [Thu, 29 Aug 2019 10:54:35 +0000 (10:54 +0000)]
[ARM] MVE Masked loads and stores
Masked loads and store fit naturally with MVE, the instructions being easily
predicated. This adds lowering for the simple cases of masked loads and stores.
It does not yet deal with widening/narrowing or pre/post inc.
The llvm masked load intrinsic will accept a "passthru" value, dictating the
values used for the zero masked lanes. In MVE the instructions write 0 to the
zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
with a select instruction to pull in the correct data after the load.
We also need to do something with unaligned loads/stores. Currently this uses a
similar method used in big endian, using an VLDRB.8 (and potentially a VREV in
BE). This does mean that the predicate mask is converted from, for example, a
v4i1 to a v16i1. The VLDR instructions are defined as using the first bit of
the relevant mask lane, so this could potentially load different results if the
predicate is little odd. As the input is a v4i1 however, I believe this is OK
and all the bits required should be set in the predicate, making the VLDRB.8
load the same data.
Differential Revision: https://reviews.llvm.org/D66534
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370329
91177308-0d34-0410-b5e6-
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Jeremy Morse [Thu, 29 Aug 2019 10:53:29 +0000 (10:53 +0000)]
[DebugInfo] LiveDebugValues should always revisit backedges if it skips them
The "join" method in LiveDebugValues does not attempt to join unseen
predecessor blocks if their out-locations aren't yet initialized, instead
the block should be re-visited later to see if any locations have changed
validity. However, because the set of blocks were all being "process"'d
once before "join" saw them, that logic in "join" was actually ignoring
legitimate out-locations on the first pass through. This meant that some
invalidated locations were not removed from the head of loops, allowing
illegal locations to persist.
Fix this by removing the run of "process" before the main join/process loop
in ExtendRanges. Now the unseen predecessors that "join" skips truly are
uninitialized, and we come back to the block at a later time to re-run
"join", see the @baz function added.
This also fixes another fault where stack/register transfers in the entry
block (or any other before-any-loop-block) had their tranfers initially
ignored, and were then never revisited. The MIR test added tests for this
behaviour.
XFail a test that exposes another bug; a fix for this is coming in D66895.
Differential Revision: https://reviews.llvm.org/D66663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370328
91177308-0d34-0410-b5e6-
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Roman Lebedev [Thu, 29 Aug 2019 10:50:09 +0000 (10:50 +0000)]
[X86][CodeGen][NFC] Delay `combineIncDecVector()` from DAGCombine to X86DAGToDAGISel
Summary:
We were previously doing it in DAGCombine.
But we also want to do `sub %x, C` -> `add %x, (sub 0, C)` for vectors in DAGCombine.
So if we had `sub %x, -1`, we'll transform it to `add %x, 1`,
which `combineIncDecVector()` will immediately transform back into `sub %x, -1`,
and here we go again...
I've marked this as NFC since not a single test changes,
but since that 'changes' DAGCombine, probably this isn't fully NFC.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: craig.topper
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370327
91177308-0d34-0410-b5e6-
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Amaury Sechet [Thu, 29 Aug 2019 10:35:51 +0000 (10:35 +0000)]
[DAGCombiner] (insert_vector_elt (vector_shuffle X, Y), (extract_vector_elt X, N), IdxC) -> (vector_shuffle X, Y)
Summary: This is beneficial when the shuffle is only used once and end up being generated in a few places when some node is combined into a shuffle.
Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370326
91177308-0d34-0410-b5e6-
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David Green [Thu, 29 Aug 2019 10:32:12 +0000 (10:32 +0000)]
[ARM] Masked load and store and predicate tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370325
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Thu, 29 Aug 2019 10:26:23 +0000 (10:26 +0000)]
[InstCombine] Shift amount reassociation in bittest: trunc-of-lshr (PR42399)
Summary:
Finally, the fold i was looking forward to :)
The legality check is muddy, i doubt i've groked the full generalization,
but it handles all the cases i care about, and can come up with:
https://rise4fun.com/Alive/26j
I.e. we can perform the fold if **any** of the following is true:
* The shift amount is either zero or one less than widest bitwidth
* Either of the values being shifted has at most lowest bit set
* The value that is being shifted by `shl` (which is not truncated) should have no less leading zeros than the total shift amount;
* The value that is being shifted by `lshr` (which **is** truncated) should have no less leading zeros than the widest bit width minus total shift amount minus one
I strongly suspect there is some better generalization, but i'm not aware of it as of right now.
For now i also avoided using actual `computeKnownBits()`, but restricted it to constants.
Reviewers: spatel, nikic, xbolva00
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370324
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 29 Aug 2019 10:11:34 +0000 (10:11 +0000)]
LegalizeSetCCCondCode - Reduce scope of NeedSwap to fix cppcheck warning. NFCI.
No need for this to be defined outside the only switch case its used in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370320
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 29 Aug 2019 10:08:45 +0000 (10:08 +0000)]
Fix variable set but no used warnings on NDEBUG builds. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370319
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 29 Aug 2019 09:58:47 +0000 (09:58 +0000)]
Fix variable set but no used warning on NDEBUG builds. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370317
91177308-0d34-0410-b5e6-
96231b3b80d8
Martin Storsjo [Thu, 29 Aug 2019 09:00:14 +0000 (09:00 +0000)]
[COFF] Add a ResourceSectionRef method for getting the data entry, print it in llvm-readobj
Differential Revision: https://reviews.llvm.org/D66819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370311
91177308-0d34-0410-b5e6-
96231b3b80d8
Martin Storsjo [Thu, 29 Aug 2019 08:59:56 +0000 (08:59 +0000)]
[COFF] Add a bounds checking helper for iterating a coff_resource_dir_table
Instead of blindly incrementing pointers in llvm-readobj, use this
helper, which does bounds checking against the available section
data.
Differential Revision: https://reviews.llvm.org/D66818
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370310
91177308-0d34-0410-b5e6-
96231b3b80d8
Martin Storsjo [Thu, 29 Aug 2019 08:59:41 +0000 (08:59 +0000)]
[COFF] Fix error handling in ResourceSectionRef
Previously, the expression (Reader.readFoo()) was expanded twice,
triggering asserts as one of the Error types ends up not checked
(and as it was expanded twice, the method would end up called twice
if it failed first).
Differential Revision: https://reviews.llvm.org/D66817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370309
91177308-0d34-0410-b5e6-
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Martin Storsjo [Thu, 29 Aug 2019 08:59:31 +0000 (08:59 +0000)]
[llvm-readobj] Print the resource type textually for .res files
This already is done when dumping resources from coff objects.
Differential Revision: https://reviews.llvm.org/D66816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370308
91177308-0d34-0410-b5e6-
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Martin Storsjo [Thu, 29 Aug 2019 08:59:05 +0000 (08:59 +0000)]
[llvm-readobj] Remove a leftover string trim operation. NFC.
This became unnecessary in SVN r359153.
Differential Revision: https://reviews.llvm.org/D66815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370307
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 29 Aug 2019 06:36:16 +0000 (06:36 +0000)]
[X86] Remove isel patterns with X86VBroadcast+scalar_to_vector+load.
The DAG should have these as X86VBroadcast+load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370299
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 29 Aug 2019 06:02:11 +0000 (06:02 +0000)]
[X86] Remove some unneeded X86VBroadcast isel patterns that have larger than 128 bit input types.
We should always be shrinking the input to 128 bits or smaller
when the node is created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370296
91177308-0d34-0410-b5e6-
96231b3b80d8
Hideto Ueno [Thu, 29 Aug 2019 05:52:00 +0000 (05:52 +0000)]
[Attributor] Deduce "noalias" attribute
Summary:
This patch adds very basic deduction for noalias.
Reviewers: jdoerfert, sstefan1
Reviewed By: jdoerfert
Tags: LLVM
Differential Revision: https://reviews.llvm.org/D66207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370295
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 29 Aug 2019 05:48:48 +0000 (05:48 +0000)]
[X86] Add a DAG combine to combine INSERTPS and VBROADCAST of a scalar load. Remove corresponding isel patterns.
We had an isel pattern to perform this, but its better to
do it in DAG combine as a simplification. This also fixes the lack
of patterns for AVX512 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370294
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Craig Topper [Thu, 29 Aug 2019 05:13:56 +0000 (05:13 +0000)]
[X86] Make inline assembly 'x' and 'v' constraints work for f128.
Including a type legalizer fix to make bitcast operand promotion
work correctly when getSoftenedFloat returns f128 instead of i128.
Fixes PR43157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370293
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Florian Hahn [Thu, 29 Aug 2019 04:26:29 +0000 (04:26 +0000)]
[LoopUnroll] Use Lazy strategy for DTU used for MergeBlockIntoPredecessor.
We do not access the DT in the loop, so we do not have to apply updates
eagerly. We can apply them lazyly and flush them after we are done
merging blocks.
As follow-up work, we might be able to use the DTU above as well,
instead of manually updating the DT.
This brings the example from PR43134 from ~100s to ~4s for a relase +
assertions build on my machine.
Reviewers: efriedma, kuhar, asbirlea, brzycki
Reviewed By: kuhar, brzycki
Differential Revision: https://reviews.llvm.org/D66911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370292
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Vitaly Buka [Thu, 29 Aug 2019 02:36:48 +0000 (02:36 +0000)]
[ObjectYAML] Fix lifetime issue in dumpDebugLines
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66901
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370289
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Johannes Doerfert [Thu, 29 Aug 2019 01:29:44 +0000 (01:29 +0000)]
[Attributor] Improve messages in iteration verify mode
When we now verify the iteration count we will see the actual count
and the expected count before the assertion is triggered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370285
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Johannes Doerfert [Thu, 29 Aug 2019 01:28:30 +0000 (01:28 +0000)]
[Attributor][NFC] Add const to map key
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370284
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Johannes Doerfert [Thu, 29 Aug 2019 01:26:58 +0000 (01:26 +0000)]
[Attributor][Fix] Indicate change correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370283
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Johannes Doerfert [Thu, 29 Aug 2019 01:26:09 +0000 (01:26 +0000)]
[Attributor] Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370282
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Matt Arsenault [Thu, 29 Aug 2019 01:13:47 +0000 (01:13 +0000)]
AMDGPU: Don't use frame virtual registers
SGPR spills aren't really handled after SILowerSGPRSpills. In order to
directly control what happens if the scavenger needs to spill, the
scavenger needs to be used directly. There is an alternative to
spilling in these contexts anyway since the frame register can be
increment and restored.
This does present another possible issue if spilling is needed for the
unused carry out if an add is needed. I think this can be avoided by
using a scalar add (although that clobbers SCC, which happens anyway).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370281
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Matt Arsenault [Thu, 29 Aug 2019 01:13:41 +0000 (01:13 +0000)]
GlobalISel/TableGen: Handle setcc patterns
This is a special case because one node maps to two different G_
instructions, and the operand order is changed.
This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually
selected for now since it has the SALU and VALU complication to deal
with.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370280
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Richard Trieu [Thu, 29 Aug 2019 00:46:57 +0000 (00:46 +0000)]
Add requirement to test.
-debug-only option for llc is only available in debug builds so
"REQUIRES: asserts" is needed in the tes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370279
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Craig Topper [Wed, 28 Aug 2019 23:45:10 +0000 (23:45 +0000)]
[X86] Fix a couple isel patterns to not shrink a volatile load.
Also add a FIXME because I'm not sure why these patterns exist. Looks like a missing combine.
And another FIXME because the AVX512 equivalent one of the patterns is missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370276
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Shiva Chen [Wed, 28 Aug 2019 23:40:37 +0000 (23:40 +0000)]
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
The patch fixed the issue that RV64 didn't clear the upper bits
when return complex floating value with lp64 ABI.
float _Complex
complex_add(float _Complex a, float _Complex b)
{
return a + b;
}
RealResult = zero_extend(RealA + RealB)
ImageResult = ImageA + ImageB
Return (RealResult | (ImageResult << 32))
The patch introduces shouldExtendTypeInLibCall target hook to suppress
the AssertZext generation when lowering floating LibCall.
Thanks to Eli's comments from the Bugzilla
https://bugs.llvm.org/show_bug.cgi?id=42820
Differential Revision: https://reviews.llvm.org/D65497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370275
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Heejin Ahn [Wed, 28 Aug 2019 23:13:43 +0000 (23:13 +0000)]
[WebAssembly] Add atomic.fence instruction
Summary:
This adds `atomic.fence` instruction:
https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md#fence-operator
And we now emit the new `atomic.fence` instruction for multithread
fences, rather than the prevous `atomic.rmw` hack.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, tlively, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370272
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Tom Stellard [Wed, 28 Aug 2019 22:59:04 +0000 (22:59 +0000)]
[LLVM-C] Fix omission of INSTALL_WITH_TOOLCHAIN to llvm_add_library()
Due to a misstake with r365902 that tried to simplify the install with
toolchain logic LLVM-C.dll was no longer being installed.
Patch By: Jakob Bornecrantz
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370271
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Simon Atanasyan [Wed, 28 Aug 2019 22:32:16 +0000 (22:32 +0000)]
[mips] Add an empty line to separate different patterns. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370269
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Simon Atanasyan [Wed, 28 Aug 2019 22:32:10 +0000 (22:32 +0000)]
[mips] Fix 64-bit address loading in case of applying 32-bit mask to the result
If result of 64-bit address loading combines with 32-bit mask, LLVM
tries to optimize the code and remove "redundant" loading of upper
32-bits of the address. It leads to incorrect code on MIPS64 targets.
MIPS backend creates the following chain of commands to load 64-bit
address in the `MipsTargetLowering::getAddrNonPICSym64` method:
```
(add (shl (add (shl (add %highest(sym), %higher(sym)),
16),
%hi(sym)),
16),
%lo(%sym))
```
If the mask presents, LLVM decides to optimize the chain of commands. It
really does not make sense to load upper 32-bits because the 0x0fffffff
mask anyway clears them. After removing redundant commands we get this
chain:
```
(add (shl (%hi(sym), 16), %lo(%sym))
```
There is no patterns matched `(MipsHi (i64 symbol))`. Due a bug in `SYM_32`
predicate definition, backend incorrectly selects a pattern for a 32-bit
symbols and uses the `lui` instruction for loading `%hi(sym)`.
As a result we get incorrect set of instructions with unnecessary 16-bit
left shifting:
```
lui at,0x0
R_MIPS_HI16 foo
dsll at,at,0x10
daddiu at,at,0
R_MIPS_LO16 foo
```
This patch resolves two problems:
- Fix `SYM_32/SYM_64` predicates to prevent selection of patterns dedicated
to 32-bit symbols in case of using N64 ABI.
- Add missed patterns for 64-bit symbols for `%hi/%lo`.
Fix PR42736.
Differential Revision: https://reviews.llvm.org/D66228
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370268
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Jessica Paquette [Wed, 28 Aug 2019 22:03:05 +0000 (22:03 +0000)]
Add tie-breaker for register class sorting in getSuperRegForSubReg
llvm::stable_sort is apparently not sufficient.
Use the same tie-breaker/sorting style as TopoOrderRC fix bot failures.
E.g.
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/19401/steps/test-check-all/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370267
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Artur Pilipenko [Wed, 28 Aug 2019 21:27:50 +0000 (21:27 +0000)]
Fix for "DICompileUnit not listed in llvm.dbg.cu" verification error after ...
...cloning a function from a different module
Currently when a function with debug info is cloned from a different module, the
cloned function may have hanging DICompileUnits, so that the module with the
cloned function fails debug info verification.
The proposed fix inserts all DICompileUnits reachable from the cloned function
to "llvm.dbg.cu" metadata operands of the cloned function module.
Reviewed By: aprantl, efriedma
Differential Revision: https://reviews.llvm.org/D66510
Patch by Oleg Pliss (Oleg.Pliss@azul.com)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370265
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Jason Liu [Wed, 28 Aug 2019 20:59:17 +0000 (20:59 +0000)]
[llvm-readobj][XCOFF][NFC] Add return statement to avoid -Wimplicit-fallthrough warning
This is to fix the commit in r370097.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370260
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Julian Lettner [Wed, 28 Aug 2019 20:40:55 +0000 (20:40 +0000)]
[ASan] Make insertion of version mismatch guard configurable
By default ASan calls a versioned function
`__asan_version_mismatch_check_vXXX` from the ASan module constructor to
check that the compiler ABI version and runtime ABI version are
compatible. This ensures that we get a predictable linker error instead
of hard-to-debug runtime errors.
Sometimes, however, we want to skip this safety guard. This new command
line option allows us to do just that.
rdar://
47891956
Reviewed By: kubamracek
Differential Revision: https://reviews.llvm.org/D66826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370258
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James Y Knight [Wed, 28 Aug 2019 20:35:50 +0000 (20:35 +0000)]
Ignore object files that lack coverage information.
Before this change, if multiple binary files were presented, all of them must have been instrumented or the load would fail with coverage_map_error::no_data_found.
Patch by Dean Sturtevant.
Differential Revision: https://reviews.llvm.org/D66763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370257
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Philip Reames [Wed, 28 Aug 2019 20:27:39 +0000 (20:27 +0000)]
Use the handle --check-prefixes mechanism to de-verbosify a couple atomics tests [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370256
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Jessica Paquette [Wed, 28 Aug 2019 20:12:31 +0000 (20:12 +0000)]
[GlobalISel] Import patterns containing SUBREG_TO_REG
Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns.
- Split `inferSuperRegisterClass` into two functions, one which tries to use
an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that
doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause
for the split.
- Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and
update it.
- Update impacted tests in the AArch64 and X86 backends.
This is kind of a hit/miss for code size improvements/regressions. E.g. in
add-ext.ll, we now get some identity copies. This isn't really anything the
importer can handle, since it's caused by a later pass introducing the copy for
the sake of correctness.
Differential Revision: https://reviews.llvm.org/D66769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370254
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Nico Weber [Wed, 28 Aug 2019 19:38:59 +0000 (19:38 +0000)]
gn build: Merge r370249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370251
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Scott Linder [Wed, 28 Aug 2019 19:38:15 +0000 (19:38 +0000)]
[AMDGPU] Fix bug when calculating user_spgr_count for Code Object V3 assembler
Stop counting explicitly disabled user_spgr's in the user_sgpr_count field of the kernel descriptor.
Differential Revision: https://reviews.llvm.org/D66900
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370250
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Sanjay Patel [Wed, 28 Aug 2019 18:58:06 +0000 (18:58 +0000)]
[InstCombine] clean up wrap propagation for reassociated ops; NFCI
Always true/false checks were flagged by static analysis;
https://bugs.llvm.org/show_bug.cgi?id=43143
I have not confirmed the logic difference in propagating nsw vs. nuw,
but presumably we would have noticed a bug by now if that was wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370248
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Pirama Arumuga Nainar [Wed, 28 Aug 2019 17:43:14 +0000 (17:43 +0000)]
[ValueMapper] NFC: Remove dead code to pause metadata mapping
Summary:
This functionality was added when Mapper::mapMetadata was recursive. It
is no longer needed after r265456, which switched it to be iterative.
Reviewers: dexonsmith, srhines
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66860
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370236
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Craig Topper [Wed, 28 Aug 2019 17:18:56 +0000 (17:18 +0000)]
[X86][ReleaseNotes] Add a note about the switch to widening legalization for narrow vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370233
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Johannes Doerfert [Wed, 28 Aug 2019 16:58:52 +0000 (16:58 +0000)]
[Attributor] Regularly clear dependences to remove spurious ones
As dependences between abstract attributes can become stale, e.g., if
one was sufficient to imply another one at some point but it has since
been wakened to the point it is not usable for the formerly implied one.
To weed out spurious dependences, and thereby eliminate unneeded
updates, we introduce an option to determine how often the dependence
cache is cleared and recomputed during the fixpoint iteration.
Note that the initial value was determined such that we see a positive
result on our tests.
Differential Revision: https://reviews.llvm.org/D63315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370230
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Kevin P. Neal [Wed, 28 Aug 2019 16:33:36 +0000 (16:33 +0000)]
[FPEnv] Add fptosi and fptoui constrained intrinsics.
This implements constrained floating point intrinsics for FP to signed and
unsigned integers.
Quoting from D32319:
The purpose of the constrained intrinsics is to force the optimizer to
respect the restrictions that will be necessary to support things like the
STDC FENV_ACCESS ON pragma without interfering with optimizations when
these restrictions are not needed.
Reviewed by: Andrew Kaylor, Craig Topper, Hal Finkel, Cameron McInally, Roman Lebedev, Kit Barton
Approved by: Craig Topper
Differential Revision: http://reviews.llvm.org/D63782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370228
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Jessica Paquette [Wed, 28 Aug 2019 16:19:01 +0000 (16:19 +0000)]
[AArch64][GlobalISel] Fall back when translating musttail calls
These are currently translated as normal functions calls in AArch64.
Until we have proper tail call lowering, we shouldn't translate these.
Differential Revision: https://reviews.llvm.org/D66842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370225
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Simon Pilgrim [Wed, 28 Aug 2019 16:06:33 +0000 (16:06 +0000)]
Reduce scope of variable only used in a local pattern match. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370224
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David Bolvansky [Wed, 28 Aug 2019 16:00:15 +0000 (16:00 +0000)]
[NFC] Added more tests for D66651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370222
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Craig Topper [Wed, 28 Aug 2019 15:40:34 +0000 (15:40 +0000)]
[InstCombine] Disable recursion in foldGEPICmp for vector pointer GEPs
Due to missing vector support in this function, recursion can
generate worse code in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370221
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Simon Pilgrim [Wed, 28 Aug 2019 15:19:49 +0000 (15:19 +0000)]
Fix uninitialized variable warning in cppcheck. NFCI.
InstCombiner::MaxArraySizeForCombine is set outside the constructor so we need to ensure it has a default initialization value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370220
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David Bolvansky [Wed, 28 Aug 2019 15:04:48 +0000 (15:04 +0000)]
[NFC] Added a comment to avoid possible confusion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370217
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Ryan Taylor [Wed, 28 Aug 2019 15:00:45 +0000 (15:00 +0000)]
[AMDGPU] Adjust number of SGPRs available in Calling Convention
This reduces the number of SGPRs due to some concerns about running
out of SGPRs if you make all the SGPRs that aren't reserved available
for the calling convention.
Change-Id: Idb4ca4dc72f5b6808cb524ff7270915a8de5b4c1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370215
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Simon Pilgrim [Wed, 28 Aug 2019 14:37:44 +0000 (14:37 +0000)]
Remove duplicate 'BitWidth' variable. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370212
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Johannes Doerfert [Wed, 28 Aug 2019 14:09:14 +0000 (14:09 +0000)]
[Attributor] Restrict liveness and return information to functions
Summary:
Until we have proper call-site information we should not recompute
liveness and return information for each call site. This patch directly
uses the function versions and introduces TODOs at the usage sites.
The required iterations to get to the fixpoint are most of the time
reduced by this change and we always avoid work duplication.
Reviewers: sstefan1, uenoku
Subscribers: hiraditya, bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370208
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Simon Pilgrim [Wed, 28 Aug 2019 14:05:38 +0000 (14:05 +0000)]
InstCombiner::visitSelectInst - rename Pred to MinMaxPred to stop shadow variable warning. NFCI.
We have a lot of Predicate variables, all similarly named....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370207
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Vlad Tsyrklevich [Wed, 28 Aug 2019 14:04:09 +0000 (14:04 +0000)]
Reland "[yaml2obj] - Don't allow setting StOther and Other/Visibility at the same time."
This relands this commit, I mistakenly reverted the original change
thinking it was the cause of the observed MSan failures but it was not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370206
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Hans Wennborg [Wed, 28 Aug 2019 13:55:10 +0000 (13:55 +0000)]
[SelectionDAG] Don't generate libcalls for wide shifts on Windows (PR42711)
Neither libgcc or compiler-rt are usually used on Windows, so these
functions can't be called.
Differential revision: https://reviews.llvm.org/D66880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370204
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Amaury Sechet [Wed, 28 Aug 2019 13:52:32 +0000 (13:52 +0000)]
[X86] Add test for rotate combining when add X, X is used instead of shl X, 1. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370203
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Vlad Tsyrklevich [Wed, 28 Aug 2019 13:15:08 +0000 (13:15 +0000)]
Revert "[yaml2obj] - Don't allow setting StOther and Other/Visibility at the same time."
This reverts commit r370032, it was causing check-llvm failures on
sanitizer-x86_64-linux-bootstrap-msan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370198
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Simon Pilgrim [Wed, 28 Aug 2019 12:48:41 +0000 (12:48 +0000)]
[DAGCombine] Fix cppcheck shadow variable warning. NFCI.
We already have an outer Ops variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370197
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Simon Atanasyan [Wed, 28 Aug 2019 12:35:53 +0000 (12:35 +0000)]
[mips] Use less registers to load address of TargetExternalSymbol
There is no pattern matched `add hi, (MipsLo texternalsym)`. As a result,
loading an address of 32-bit symbol requires two registers and one more
additional instruction:
```
addiu $1, $zero, %lo(foo)
lui $2, %hi(foo)
addu $25, $2, $1
```
This patch adds the missed pattern and enables generation more effective
set of instructions:
```
lui $1, %hi(foo)
addiu $25, $1, %lo(foo)
```
Differential Revision: https://reviews.llvm.org/D66771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370196
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Amaury Sechet [Wed, 28 Aug 2019 12:00:06 +0000 (12:00 +0000)]
[TargetLowering] Add buildLegalVectorShuffle facility to help build legal shuffles
Summary: There are at least 2 ways to express the same shuffle. Various pieces of code explicit check for both option, but other places do not when they would benefit from doing it. This patches refactor the codebase to use buildLegalVectorShuffle in order to make that behavior more consistent.
Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri
Subscribers: javed.absar, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370190
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Simon Pilgrim [Wed, 28 Aug 2019 11:50:36 +0000 (11:50 +0000)]
[DAGCombine] Remove LoadedSlice::Cost default 'ForCodeSize' constructor arguments. NFCI.
These were always being passed in and it allowed me to add the explicit tag to stop a cppcheck warning about 1 argument constructors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370189
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Nico Weber [Wed, 28 Aug 2019 11:42:20 +0000 (11:42 +0000)]
gn build: Merge r370187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370188
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David Green [Wed, 28 Aug 2019 11:37:31 +0000 (11:37 +0000)]
[ARM] Move MVEVPTBlockPass to a separate file. NFC
This just pulls the MVEVPTBlockPass into a separate file, as opposed to being
wrapped up in Thumb2ITBlockPass.
Differential revision: https://reviews.llvm.org/D66579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370187
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David Green [Wed, 28 Aug 2019 10:13:23 +0000 (10:13 +0000)]
[MVE] VMOVX patterns
This adds fp16 VMOVX patterns, using the same patterns as rL362482 with some
adjustments for MVE. It allows us to move fp16 registers without going into and
out of gprs.
VMOVX is able to move the top bits from a fp16 in a fp reg into the bottom bits
of another register, zeroing the rest. This can be used for odd MVE register
lanes. The top bits are not read by fp16 instructions, so no move is required
there if we are dealing with even lanes.
Differential revision: https://reviews.llvm.org/D66793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370184
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Hans Wennborg [Wed, 28 Aug 2019 09:21:56 +0000 (09:21 +0000)]
[LLVM-C] Fix ByVal Attribute crashing
With the introduction of the typed byval attribute change there was no
way that the LLVM-C API could create the correct class Attribute. If a
program that uses the C API creates a ByVal attribute and annotates a
function with that attribute LLVM will crash when it assembles or write
that module containing the function out as bitcode.
This change is a minimal fix to at least allow code to work, this is
because the byval change is on the 9.0 and I don't want to introduce new
LLVM-C API this late in the release cycle.
By Jakob Bornecrantz!
Differential revision: https://reviews.llvm.org/D66144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370176
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Ayal Zaks [Wed, 28 Aug 2019 09:02:23 +0000 (09:02 +0000)]
[LV] Fold tail by masking - handle reductions
Allow vectorizing loops that have reductions when tail is folded by masking.
A select is introduced in VPlan, choosing between the last value carried by the
loop-exit/live-out instruction of the reduction, and the penultimate value
carried by the reduction phi, according to the "i < n" mask of fold-tail.
This select replaces the last value as the live-out value of the loop.
Differential Revision: https://reviews.llvm.org/D66720
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370173
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Sam Parker [Wed, 28 Aug 2019 08:51:13 +0000 (08:51 +0000)]
[ARM][ParallelDSP] Change search for muls
rL369567 reverted a couple of recent changes made to ARMParallelDSP
because of a miscompilation error: PR43073.
The issue stemmed from an underlying bug that was caused by adding
muls into a reduction before it was proved that they could be executed
in parallel with another mul.
Most of the changes here are from the previously reverted commits.
The additional changes have been made area:
1) The Search function now doesn't insert any muls into the Reduction
object. That now happens once the search has successfully finished.
2) For any muls added into the reduction but that weren't paired, we
accumulate their values as an input into the smlad.
Differential Revision: https://reviews.llvm.org/D66660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370171
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David Bolvansky [Wed, 28 Aug 2019 08:42:40 +0000 (08:42 +0000)]
[NFC] Unbreak tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370170
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David Bolvansky [Wed, 28 Aug 2019 08:40:45 +0000 (08:40 +0000)]
[NFC] Updated test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370169
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David Bolvansky [Wed, 28 Aug 2019 08:28:20 +0000 (08:28 +0000)]
Annotate return values of allocation functions with dereferenceable_or_null
Summary:
Example
define dso_local noalias i8* @_Z6maixxnv() local_unnamed_addr #0 {
entry:
%call = tail call noalias dereferenceable_or_null(64) i8* @malloc(i64 64) #6
ret i8* %call
}
Reviewers: jdoerfert
Reviewed By: jdoerfert
Subscribers: aaron.ballman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370168
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Yi Kong [Wed, 28 Aug 2019 06:37:22 +0000 (06:37 +0000)]
[llvm-objdump] Add the missing ARMv8 subarch detection
Differential Revision: https://reviews.llvm.org/D66849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370163
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Fangrui Song [Wed, 28 Aug 2019 03:12:40 +0000 (03:12 +0000)]
[LoopFusion] Fix another -Wunused-function in -DLLVM_ENABLE_ASSERTIONS=off build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370156
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Matt Arsenault [Wed, 28 Aug 2019 02:11:03 +0000 (02:11 +0000)]
AMDGPU/GlobalISel: Fix constraining scalar and/or/xor
If the result register already had a register class assigned, the
sources may not have been properly constrained.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370150
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Richard Trieu [Wed, 28 Aug 2019 01:55:06 +0000 (01:55 +0000)]
Revert r370105 - Update two x86 datalayouts for r370083, looks like racing commits
r370083 has been reverted, which this change depends on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370147
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Vedant Kumar [Wed, 28 Aug 2019 01:39:36 +0000 (01:39 +0000)]
[test] Speculative fix for r369966 on llvm-clang-x86_64-win
Run the MIR pipeline in this test to completion to try and avoid a "Bad
machine code" error.
Build failure:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20190826/688338.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370145
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Vlad Tsyrklevich [Wed, 28 Aug 2019 01:08:54 +0000 (01:08 +0000)]
Revert "Change the X86 datalayout to add three address spaces for 32 bit signed,"
This reverts commit r370083 because it caused check-lld failures on
sanitizer-x86_64-linux-fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370142
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Matt Arsenault [Wed, 28 Aug 2019 00:58:24 +0000 (00:58 +0000)]
AMDGPU/GlobalISel: Implement addrspacecast for 32-bit constant addrspace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370140
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Philip Reames [Tue, 27 Aug 2019 23:36:31 +0000 (23:36 +0000)]
[NFC] Assert preconditions and merge all users into one codepath in Loads.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370128
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Craig Topper [Tue, 27 Aug 2019 21:38:56 +0000 (21:38 +0000)]
[InstCombine] Disable some portions of foldGEPICmp for GEPs that return a vector of pointers. Fix other portions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370114
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Luis Marques [Tue, 27 Aug 2019 21:37:57 +0000 (21:37 +0000)]
[RISCV] Implement RISCVRegisterInfo::getPointerRegClass
Fixes bug 43041
Differential Revision: https://reviews.llvm.org/D66752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370113
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Craig Topper [Tue, 27 Aug 2019 21:31:44 +0000 (21:31 +0000)]
[Analysis] Improve EmitGEPOffset handling of vector GEPs with scalar indices.
This patch splats the scalar index if necessary before using it
in any integer casts or other arithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370112
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