From: Craig Topper <craig.topper@intel.com>
Date: Mon, 11 Dec 2017 08:33:20 +0000 (+0000)
Subject: [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ff09090aacc073a9c245e88476b0189f9ed3dd05;p=llvm

[DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors.

We should probably also fold (mulhs/u X, 1) for vectors, but that's harder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320344 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2170670a0b6..4cc86ed2d36 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3099,6 +3099,14 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) {
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
+  if (VT.isVector()) {
+    // fold (mulhs x, 0) -> 0
+    if (ISD::isBuildVectorAllZeros(N1.getNode()))
+      return N1;
+    if (ISD::isBuildVectorAllZeros(N0.getNode()))
+      return N0;
+  }
+
   // fold (mulhs x, 0) -> 0
   if (isNullConstant(N1))
     return N1;
@@ -3138,6 +3146,14 @@ SDValue DAGCombiner::visitMULHU(SDNode *N) {
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
+  if (VT.isVector()) {
+    // fold (mulhu x, 0) -> 0
+    if (ISD::isBuildVectorAllZeros(N1.getNode()))
+      return N1;
+    if (ISD::isBuildVectorAllZeros(N0.getNode()))
+      return N0;
+  }
+
   // fold (mulhu x, 0) -> 0
   if (isNullConstant(N1))
     return N1;
diff --git a/test/CodeGen/X86/pr34855.ll b/test/CodeGen/X86/pr34855.ll
index ee4428908a2..746d1ff56cc 100644
--- a/test/CodeGen/X86/pr34855.ll
+++ b/test/CodeGen/X86/pr34855.ll
@@ -8,18 +8,13 @@ define void @PR34855(<2 x i32> *%p0, <2 x i32> *%p1, <2 x i32> *%p2) {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; X86-NEXT:    movlps %xmm0, (%eax)
+; X86-NEXT:    movsd %xmm0, (%eax)
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: PR34855:
 ; X64:       # %bb.0:
-; X64-NEXT:    movslq 4(%rdi), %rax
-; X64-NEXT:    movq %rax, %xmm0
-; X64-NEXT:    movslq (%rdi), %rax
-; X64-NEXT:    movq %rax, %xmm1
-; X64-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
-; X64-NEXT:    movq %xmm0, (%rdx)
+; X64-NEXT:    movq (%rdi), %rax
+; X64-NEXT:    movq %rax, (%rdx)
 ; X64-NEXT:    retq
   %tmp = load <2 x i32>, <2 x i32>* %p0, align 8
   %tmp1 = load <2 x i32>, <2 x i32>* %p1, align 8