From: Simon Pilgrim Date: Tue, 18 Dec 2018 09:33:25 +0000 (+0000) Subject: [TargetLowering] Fallback from SimplifyDemandedVectorElts to SimplifyDemandedBits X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=fe8acf3ad35c896fafaf0f9ddee5f643474f00a3;p=llvm [TargetLowering] Fallback from SimplifyDemandedVectorElts to SimplifyDemandedBits For opcodes not covered by SimplifyDemandedVectorElts, SimplifyDemandedBits might be able to help now that it supports demanded elts as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349466 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 8ac1a962a8e..4c551d5b231 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1894,10 +1894,17 @@ bool TargetLowering::SimplifyDemandedVectorElts( return true; break; default: { - if (Op.getOpcode() >= ISD::BUILTIN_OP_END) + if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef, KnownZero, TLO, Depth)) return true; + } else { + KnownBits Known; + APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits); + if (SimplifyDemandedBits(Op, DemandedBits, DemandedEltMask, Known, TLO, + Depth, AssumeSingleUse)) + return true; + } break; } } diff --git a/test/CodeGen/X86/known-bits-vector.ll b/test/CodeGen/X86/known-bits-vector.ll index d86f603b69e..d3e4843f4ab 100644 --- a/test/CodeGen/X86/known-bits-vector.ll +++ b/test/CodeGen/X86/known-bits-vector.ll @@ -499,14 +499,12 @@ declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone define <4 x i32> @knownbits_umax_shuffle_ashr(<4 x i32> %a0) { ; X32-LABEL: knownbits_umax_shuffle_ashr: ; X32: # %bb.0: -; X32-NEXT: vpmaxud {{\.LCPI.*}}, %xmm0, %xmm0 -; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,2] +; X32-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-NEXT: retl ; ; X64-LABEL: knownbits_umax_shuffle_ashr: ; X64: # %bb.0: -; X64-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0 -; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,2] +; X64-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-NEXT: retq %1 = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> ) %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> diff --git a/test/CodeGen/X86/shrink_vmul-widen.ll b/test/CodeGen/X86/shrink_vmul-widen.ll index 3c047dae80a..7a24743d562 100644 --- a/test/CodeGen/X86/shrink_vmul-widen.ll +++ b/test/CodeGen/X86/shrink_vmul-widen.ll @@ -2254,11 +2254,9 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-AVX1-NEXT: vpinsrd $3, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload ; X86-AVX1-NEXT: vmovd {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 # 4-byte Folded Reload ; X86-AVX1-NEXT: # xmm2 = mem[0],zero,zero,zero -; X86-AVX1-NEXT: movl $8199, %eax # imm = 0x2007 -; X86-AVX1-NEXT: vmovd %eax, %xmm3 -; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [8199,8199,8199,8199] -; X86-AVX1-NEXT: vpmulld %xmm4, %xmm0, %xmm0 -; X86-AVX1-NEXT: vpmulld %xmm4, %xmm1, %xmm1 +; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [8199,8199,8199,8199] +; X86-AVX1-NEXT: vpmulld %xmm3, %xmm0, %xmm0 +; X86-AVX1-NEXT: vpmulld %xmm3, %xmm1, %xmm1 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vpmulld %xmm3, %xmm2, %xmm1 ; X86-AVX1-NEXT: vmovd %xmm1, (%eax) @@ -2331,8 +2329,6 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-AVX2-NEXT: vmovd %edx, %xmm0 ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [8199,8199,8199,8199,8199,8199,8199,8199] ; X86-AVX2-NEXT: vpmulld %ymm2, %ymm1, %ymm1 -; X86-AVX2-NEXT: movl $8199, %eax # imm = 0x2007 -; X86-AVX2-NEXT: vmovd %eax, %xmm2 ; X86-AVX2-NEXT: vpmulld %xmm2, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, (%eax) ; X86-AVX2-NEXT: vmovdqa %ymm1, (%eax) @@ -2497,12 +2493,10 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-AVX1-NEXT: vpinsrd $1, %r11d, %xmm2, %xmm2 ; X64-AVX1-NEXT: vpinsrd $2, %r10d, %xmm2, %xmm2 ; X64-AVX1-NEXT: vpinsrd $3, %r9d, %xmm2, %xmm2 +; X64-AVX1-NEXT: vpmulld %xmm1, %xmm2, %xmm2 +; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 +; X64-AVX1-NEXT: vmovd %r8d, %xmm2 ; X64-AVX1-NEXT: vpmulld %xmm1, %xmm2, %xmm1 -; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 -; X64-AVX1-NEXT: vmovd %r8d, %xmm1 -; X64-AVX1-NEXT: movl $8199, %eax # imm = 0x2007 -; X64-AVX1-NEXT: vmovd %eax, %xmm2 -; X64-AVX1-NEXT: vpmulld %xmm2, %xmm1, %xmm1 ; X64-AVX1-NEXT: vmovd %xmm1, (%rax) ; X64-AVX1-NEXT: vmovaps %ymm0, (%rax) ; X64-AVX1-NEXT: popq %rbx @@ -2566,8 +2560,6 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-AVX2-NEXT: vmovd %edx, %xmm0 ; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [8199,8199,8199,8199,8199,8199,8199,8199] ; X64-AVX2-NEXT: vpmulld %ymm2, %ymm1, %ymm1 -; X64-AVX2-NEXT: movl $8199, %eax # imm = 0x2007 -; X64-AVX2-NEXT: vmovd %eax, %xmm2 ; X64-AVX2-NEXT: vpmulld %xmm2, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, (%rax) ; X64-AVX2-NEXT: vmovdqa %ymm1, (%rax) diff --git a/test/CodeGen/X86/shrink_vmul.ll b/test/CodeGen/X86/shrink_vmul.ll index 6e9dc6020ce..97290730d90 100644 --- a/test/CodeGen/X86/shrink_vmul.ll +++ b/test/CodeGen/X86/shrink_vmul.ll @@ -2245,11 +2245,9 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-AVX1-NEXT: vpinsrd $3, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload ; X86-AVX1-NEXT: vmovd {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 # 4-byte Folded Reload ; X86-AVX1-NEXT: # xmm2 = mem[0],zero,zero,zero -; X86-AVX1-NEXT: movl $8199, %eax # imm = 0x2007 -; X86-AVX1-NEXT: vmovd %eax, %xmm3 -; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [8199,8199,8199,8199] -; X86-AVX1-NEXT: vpmulld %xmm4, %xmm0, %xmm0 -; X86-AVX1-NEXT: vpmulld %xmm4, %xmm1, %xmm1 +; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [8199,8199,8199,8199] +; X86-AVX1-NEXT: vpmulld %xmm3, %xmm0, %xmm0 +; X86-AVX1-NEXT: vpmulld %xmm3, %xmm1, %xmm1 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vpmulld %xmm3, %xmm2, %xmm1 ; X86-AVX1-NEXT: vmovd %xmm1, (%eax) @@ -2322,8 +2320,6 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X86-AVX2-NEXT: vmovd %edx, %xmm0 ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [8199,8199,8199,8199,8199,8199,8199,8199] ; X86-AVX2-NEXT: vpmulld %ymm2, %ymm1, %ymm1 -; X86-AVX2-NEXT: movl $8199, %eax # imm = 0x2007 -; X86-AVX2-NEXT: vmovd %eax, %xmm2 ; X86-AVX2-NEXT: vpmulld %xmm2, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, (%eax) ; X86-AVX2-NEXT: vmovdqa %ymm1, (%eax) @@ -2488,12 +2484,10 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-AVX1-NEXT: vpinsrd $1, %r11d, %xmm2, %xmm2 ; X64-AVX1-NEXT: vpinsrd $2, %r10d, %xmm2, %xmm2 ; X64-AVX1-NEXT: vpinsrd $3, %r9d, %xmm2, %xmm2 +; X64-AVX1-NEXT: vpmulld %xmm1, %xmm2, %xmm2 +; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 +; X64-AVX1-NEXT: vmovd %r8d, %xmm2 ; X64-AVX1-NEXT: vpmulld %xmm1, %xmm2, %xmm1 -; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 -; X64-AVX1-NEXT: vmovd %r8d, %xmm1 -; X64-AVX1-NEXT: movl $8199, %eax # imm = 0x2007 -; X64-AVX1-NEXT: vmovd %eax, %xmm2 -; X64-AVX1-NEXT: vpmulld %xmm2, %xmm1, %xmm1 ; X64-AVX1-NEXT: vmovd %xmm1, (%rax) ; X64-AVX1-NEXT: vmovaps %ymm0, (%rax) ; X64-AVX1-NEXT: popq %rbx @@ -2557,8 +2551,6 @@ define void @PR34947(<9 x i16>* %p0, <9 x i32>* %p1) nounwind { ; X64-AVX2-NEXT: vmovd %edx, %xmm0 ; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [8199,8199,8199,8199,8199,8199,8199,8199] ; X64-AVX2-NEXT: vpmulld %ymm2, %ymm1, %ymm1 -; X64-AVX2-NEXT: movl $8199, %eax # imm = 0x2007 -; X64-AVX2-NEXT: vmovd %eax, %xmm2 ; X64-AVX2-NEXT: vpmulld %xmm2, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, (%rax) ; X64-AVX2-NEXT: vmovdqa %ymm1, (%rax)