From: Kerry McLaughlin Date: Mon, 30 Sep 2019 17:10:21 +0000 (+0000) Subject: [AArch64][SVE] Implement punpk[hi|lo] intrinsics X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=fe0144dd77595d55801a20aa6f286daecdb9036c;p=llvm [AArch64][SVE] Implement punpk[hi|lo] intrinsics Summary: Adds the following two intrinsics: - int_aarch64_sve_punpkhi - int_aarch64_sve_punpklo This patch also contains a fix which allows LLVMHalfElementsVectorType to forward reference overloadable arguments. Reviewers: sdesmalen, rovka, rengolin Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, greened, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67830 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373232 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td index a81127e75e2..2a69a51603f 100644 --- a/include/llvm/IR/IntrinsicsAArch64.td +++ b/include/llvm/IR/IntrinsicsAArch64.td @@ -768,6 +768,11 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". LLVMMatchType<0>], [IntrNoMem]>; + class AdvSIMD_SVE_PUNPKHI_Intrinsic + : Intrinsic<[LLVMHalfElementsVectorType<0>], + [llvm_anyvector_ty], + [IntrNoMem]>; + // This class of intrinsics are not intended to be useful within LLVM IR but // are instead here to support some of the more regid parts of the ACLE. class Builtin_SVCVT @@ -792,4 +797,11 @@ def int_aarch64_sve_neg : AdvSIMD_Merged1VectorArg_Intrinsic; // def int_aarch64_sve_fcvtzs_i32f16 : Builtin_SVCVT<"svcvt_s32_f16_m", llvm_nxv4i32_ty, llvm_nxv8f16_ty>; + +// +// Predicate operations +// + +def int_aarch64_sve_punpkhi : AdvSIMD_SVE_PUNPKHI_Intrinsic; +def int_aarch64_sve_punpklo : AdvSIMD_SVE_PUNPKHI_Intrinsic; } diff --git a/lib/IR/Function.cpp b/lib/IR/Function.cpp index a4632762c20..5c22109ffd5 100644 --- a/lib/IR/Function.cpp +++ b/lib/IR/Function.cpp @@ -1211,8 +1211,9 @@ static bool matchIntrinsicType( } case IITDescriptor::HalfVecArgument: // If this is a forward reference, defer the check for later. - return D.getArgumentNumber() >= ArgTys.size() || - !isa(ArgTys[D.getArgumentNumber()]) || + if (D.getArgumentNumber() >= ArgTys.size()) + return IsDeferredCheck || DeferCheck(Ty); + return !isa(ArgTys[D.getArgumentNumber()]) || VectorType::getHalfElementsVectorType( cast(ArgTys[D.getArgumentNumber()])) != Ty; case IITDescriptor::SameVecWidthArgument: { diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index 0813c41dc66..cdf313db1b9 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -216,8 +216,8 @@ let Predicates = [HasSVE] in { defm UUNPKLO_ZZ : sve_int_perm_unpk<0b10, "uunpklo">; defm UUNPKHI_ZZ : sve_int_perm_unpk<0b11, "uunpkhi">; - def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">; - def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">; + defm PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo", int_aarch64_sve_punpklo>; + defm PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi", int_aarch64_sve_punpkhi>; defm MOVPRFX_ZPzZ : sve_int_movprfx_pred_zero<0b000, "movprfx">; defm MOVPRFX_ZPmZ : sve_int_movprfx_pred_merge<0b001, "movprfx">; diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index 8c8713b464e..f57e111b7e1 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -283,6 +283,11 @@ let Predicates = [HasSVE] in { // SVE pattern match helpers. //===----------------------------------------------------------------------===// +class SVE_1_Op_Pat +: Pat<(vtd (op vt1:$Op1)), + (inst $Op1)>; + class SVE_3_Op_Pat : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)), @@ -4280,6 +4285,14 @@ class sve_int_perm_punpk let Inst{3-0} = Pd; } +multiclass sve_int_perm_punpk { + def NAME : sve_int_perm_punpk; + + def : SVE_1_Op_Pat(NAME)>; + def : SVE_1_Op_Pat(NAME)>; + def : SVE_1_Op_Pat(NAME)>; +} + class sve_int_rdffr_pred : I<(outs PPR8:$Pd), (ins PPRAny:$Pg), asm, "\t$Pd, $Pg/z", diff --git a/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll b/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll new file mode 100644 index 00000000000..d918d432ae6 --- /dev/null +++ b/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll @@ -0,0 +1,65 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s + +; +; PUNPKHI +; + +define @punpkhi_b16( %a) { +; CHECK-LABEL: punpkhi_b16 +; CHECK: punpkhi p0.h, p0.b +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.punpkhi.nxv8i1( %a) + ret %res +} + +define @punpkhi_b8( %a) { +; CHECK-LABEL: punpkhi_b8 +; CHECK: punpkhi p0.h, p0.b +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.punpkhi.nxv4i1( %a) + ret %res +} + +define @punpkhi_b4( %a) { +; CHECK-LABEL: punpkhi_b4 +; CHECK: punpkhi p0.h, p0.b +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.punpkhi.nxv2i1( %a) + ret %res +} + +; +; PUNPKLO +; + +define @punpklo_b16( %a) { +; CHECK-LABEL: punpklo_b16 +; CHECK: punpklo p0.h, p0.b +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.punpklo.nxv8i1( %a) + ret %res +} + +define @punpklo_b8( %a) { +; CHECK-LABEL: punpklo_b8 +; CHECK: punpklo p0.h, p0.b +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.punpklo.nxv4i1( %a) + ret %res +} + +define @punpklo_b4( %a) { +; CHECK-LABEL: punpklo_b4 +; CHECK: punpklo p0.h, p0.b +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.punpklo.nxv2i1( %a) + ret %res +} + +declare @llvm.aarch64.sve.punpkhi.nxv8i1() +declare @llvm.aarch64.sve.punpkhi.nxv4i1() +declare @llvm.aarch64.sve.punpkhi.nxv2i1() + +declare @llvm.aarch64.sve.punpklo.nxv8i1() +declare @llvm.aarch64.sve.punpklo.nxv4i1() +declare @llvm.aarch64.sve.punpklo.nxv2i1()