From: Rafael Espindola <rafael.espindola@gmail.com>
Date: Wed, 28 Jun 2017 14:59:30 +0000 (+0000)
Subject: Don't repeat name in comments. 80 columns. NFC.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=fd486726d15070a999d91abd17901a1dcb90f3d2;p=llvm

Don't repeat name in comments. 80 columns. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306548 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h b/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
index 0f5b765c769..4293dcba955 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h
@@ -16,53 +16,47 @@ namespace llvm {
 namespace AArch64 {
 
 enum Fixups {
-  // fixup_aarch64_pcrel_adr_imm21 - A 21-bit pc-relative immediate inserted into
-  // an ADR instruction.
+  // A 21-bit pc-relative immediate inserted into an ADR instruction.
   fixup_aarch64_pcrel_adr_imm21 = FirstTargetFixupKind,
 
-  // fixup_aarch64_pcrel_adrp_imm21 - A 21-bit pc-relative immediate inserted into
-  // an ADRP instruction.
+  // A 21-bit pc-relative immediate inserted into an ADRP instruction.
   fixup_aarch64_pcrel_adrp_imm21,
 
-  // fixup_aarch64_imm12 - 12-bit fixup for add/sub instructions.
-  //     No alignment adjustment. All value bits are encoded.
+  // 12-bit fixup for add/sub instructions. No alignment adjustment. All value
+  // bits are encoded.
   fixup_aarch64_add_imm12,
 
-  // fixup_aarch64_ldst_imm12_* - unsigned 12-bit fixups for load and
-  // store instructions.
+  // unsigned 12-bit fixups for load and store instructions.
   fixup_aarch64_ldst_imm12_scale1,
   fixup_aarch64_ldst_imm12_scale2,
   fixup_aarch64_ldst_imm12_scale4,
   fixup_aarch64_ldst_imm12_scale8,
   fixup_aarch64_ldst_imm12_scale16,
 
-  // fixup_aarch64_ldr_pcrel_imm19 - The high 19 bits of a 21-bit pc-relative
-  // immediate. Same encoding as fixup_aarch64_pcrel_adrhi, except this is used by
-  // pc-relative loads and generates relocations directly when necessary.
+  // The high 19 bits of a 21-bit pc-relative immediate. Same encoding as
+  // fixup_aarch64_pcrel_adrhi, except this is used by pc-relative loads and
+  // generates relocations directly when necessary.
   fixup_aarch64_ldr_pcrel_imm19,
 
   // FIXME: comment
   fixup_aarch64_movw,
 
-  // fixup_aarch64_pcrel_imm14 - The high 14 bits of a 21-bit pc-relative
-  // immediate.
+  // The high 14 bits of a 21-bit pc-relative immediate.
   fixup_aarch64_pcrel_branch14,
 
-  // fixup_aarch64_pcrel_branch19 - The high 19 bits of a 21-bit pc-relative
-  // immediate. Same encoding as fixup_aarch64_pcrel_adrhi, except this is use by
-  // b.cc and generates relocations directly when necessary.
+  // The high 19 bits of a 21-bit pc-relative immediate. Same encoding as
+  // fixup_aarch64_pcrel_adrhi, except this is use by b.cc and generates
+  // relocations directly when necessary.
   fixup_aarch64_pcrel_branch19,
 
-  // fixup_aarch64_pcrel_branch26 - The high 26 bits of a 28-bit pc-relative
-  // immediate.
+  // The high 26 bits of a 28-bit pc-relative immediate.
   fixup_aarch64_pcrel_branch26,
 
-  // fixup_aarch64_pcrel_call26 - The high 26 bits of a 28-bit pc-relative
-  // immediate. Distinguished from branch26 only on ELF.
+  // The high 26 bits of a 28-bit pc-relative immediate. Distinguished from
+  // branch26 only on ELF.
   fixup_aarch64_pcrel_call26,
 
-  // fixup_aarch64_tlsdesc_call - zero-space placeholder for the ELF
-  // R_AARCH64_TLSDESC_CALL relocation.
+  // zero-space placeholder for the ELF R_AARCH64_TLSDESC_CALL relocation.
   fixup_aarch64_tlsdesc_call,
 
   // Marker