From: Andrew M. Kuchling Date: Mon, 22 Feb 2010 15:15:21 +0000 (+0000) Subject: Merged revisions 78308 via svnmerge from X-Git-Tag: v3.2a1~1663 X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=fbd9d2fb1049f6870505c8fa8c4ed56dad9e572e;p=python Merged revisions 78308 via svnmerge from svn+ssh://pythondev@svn.python.org/python/trunk ........ r78308 | andrew.kuchling | 2010-02-22 10:13:17 -0500 (Mon, 22 Feb 2010) | 2 lines #6414: clarify description of processor endianness. Text by Alexey Shamrin; I changed 'DEC Alpha' to the more relevant 'Intel Itanium'. ........ --- diff --git a/Doc/library/struct.rst b/Doc/library/struct.rst index da8cc04573..bee154f07a 100644 --- a/Doc/library/struct.rst +++ b/Doc/library/struct.rst @@ -184,9 +184,11 @@ following table: If the first character is not one of these, ``'@'`` is assumed. -Native byte order is big-endian or little-endian, depending on the host system. -For example, Motorola and Sun processors are big-endian; Intel and DEC -processors are little-endian. +Native byte order is big-endian or little-endian, depending on the host +system. For example, Intel x86 and AMD64 (x86-64) are little-endian; +Motorola 68000 and PowerPC G5 are big-endian; ARM and Intel Itanium feature +switchable endianness (bi-endian). Use ``sys.byteorder`` to check the +endianness of your system. Native size and alignment are determined using the C compiler's ``sizeof`` expression. This is always combined with native byte order.