From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Mon, 27 Mar 2017 16:35:27 +0000 (+0000)
Subject: [GlobalISel] Add a 'getConstantVRegVal' helper.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=fb6a2d6627b042255635be7daca52fa2985b94f7;p=llvm

[GlobalISel] Add a 'getConstantVRegVal' helper.

Use it to compare immediate operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298855 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
index 4c25163c9f1..61b251e259c 100644
--- a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
+++ b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
@@ -16,6 +16,7 @@
 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
 
+#include "llvm/ADT/Optional.h"
 #include <cstdint>
 
 namespace llvm {
@@ -61,6 +62,9 @@ protected:
                                         const TargetRegisterInfo &TRI,
                                         const RegisterBankInfo &RBI) const;
 
+  Optional<int64_t> getConstantVRegVal(unsigned VReg,
+                                       const MachineRegisterInfo &MRI) const;
+
   bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
                          const MachineRegisterInfo &MRI) const;
 };
diff --git a/lib/CodeGen/GlobalISel/InstructionSelector.cpp b/lib/CodeGen/GlobalISel/InstructionSelector.cpp
index 104835c7c59..dd748613346 100644
--- a/lib/CodeGen/GlobalISel/InstructionSelector.cpp
+++ b/lib/CodeGen/GlobalISel/InstructionSelector.cpp
@@ -68,21 +68,29 @@ bool InstructionSelector::constrainSelectedInstRegOperands(
   return true;
 }
 
+Optional<int64_t>
+InstructionSelector::getConstantVRegVal(unsigned VReg,
+                                        const MachineRegisterInfo &MRI) const {
+  MachineInstr *MI = MRI.getVRegDef(VReg);
+  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
+    return None;
+
+  if (MI->getOperand(1).isImm())
+    return MI->getOperand(1).getImm();
+
+  if (MI->getOperand(1).isCImm() &&
+      MI->getOperand(1).getCImm()->getBitWidth() <= 64)
+    return MI->getOperand(1).getCImm()->getSExtValue();
+
+  return None;
+}
+
 bool InstructionSelector::isOperandImmEqual(
     const MachineOperand &MO, int64_t Value,
     const MachineRegisterInfo &MRI) const {
-  // TODO: We should also test isImm() and isCImm() too but this isn't required
-  //       until a DAGCombine equivalent is implemented.
-
-  if (MO.isReg()) {
-    MachineInstr *Def = MRI.getVRegDef(MO.getReg());
-    if (Def->getOpcode() != TargetOpcode::G_CONSTANT)
-      return false;
-    assert(Def->getOperand(1).isCImm() &&
-           "G_CONSTANT values must be constants");
-    const ConstantInt &Imm = *Def->getOperand(1).getCImm();
-    return Imm.getBitWidth() <= 64 && Imm.getSExtValue() == Value;
-  }
 
+  if (MO.getReg())
+    if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
+      return *VRegVal == Value;
   return false;
 }