From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 26 Jan 2017 07:17:58 +0000 (+0000)
Subject: [AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last DAG combin... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=facc9962a64bcbf308899e3ee0ed0c0f70c0d374;p=llvm

[AVX-512] Move the combine that runs combineBitcastForMaskedOp to the last DAG combine phase where I had originally meant to put it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293157 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 79e58ba4b03..7dc37f432db 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -29505,7 +29505,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
   // Look for vselects with LHS/RHS being bitcasted from an operation that
   // can be executed on another type. Push the bitcast to the inputs of
   // the operation. This exposes opportunities for using masking instructions.
-  if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalizeOps() &&
+  if (N->getOpcode() == ISD::VSELECT && DCI.isAfterLegalizeVectorOps() &&
       CondVT.getVectorElementType() == MVT::i1) {
     if (combineBitcastForMaskedOp(LHS, DAG, DCI))
       return SDValue(N, 0);