From: Alexandros Lamprineas <alexandros.lamprineas@arm.com>
Date: Wed, 28 Jun 2017 15:09:11 +0000 (+0000)
Subject: [AArch64] AArch64CondBrTuningPass generates wrong branch instructions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=fa3697c0b455747e1ce86006109c726bed7cff06;p=llvm

[AArch64] AArch64CondBrTuningPass generates wrong branch instructions

Some conditional branch instructions generated by this pass are checking
the wrong condition code. The instructions TBZ and TBNZ are transformed
into B.GE and B.LT instead of B.PL and B.MI respectively. They should
only be checking the Negative bit.

Differential Revision: https://reviews.llvm.org/D34743

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306550 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64CondBrTuning.cpp b/lib/Target/AArch64/AArch64CondBrTuning.cpp
index f27bc97ec3f..13bcbe4304b 100644
--- a/lib/Target/AArch64/AArch64CondBrTuning.cpp
+++ b/lib/Target/AArch64/AArch64CondBrTuning.cpp
@@ -22,7 +22,7 @@
 ///    cbz w8, .LBB1_2 -> b.eq .LBB1_2
 ///
 /// 3) sub w8, w0, w1       -> subs w8, w0, w1   ; w8 has multiple uses.
-///    tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2
+///    tbz w8, #31, .LBB6_2 -> b.pl .LBB6_2
 ///
 //===----------------------------------------------------------------------===//
 
@@ -129,11 +129,11 @@ MachineInstr *AArch64CondBrTuning::convertToCondBr(MachineInstr &MI) {
     break;
   case AArch64::TBZW:
   case AArch64::TBZX:
-    CC = AArch64CC::GE;
+    CC = AArch64CC::PL;
     break;
   case AArch64::TBNZW:
   case AArch64::TBNZX:
-    CC = AArch64CC::LT;
+    CC = AArch64CC::MI;
     break;
   }
   return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
diff --git a/test/CodeGen/AArch64/cond-br-tuning.ll b/test/CodeGen/AArch64/cond-br-tuning.ll
index 628d89e34a0..d966acbebfd 100644
--- a/test/CodeGen/AArch64/cond-br-tuning.ll
+++ b/test/CodeGen/AArch64/cond-br-tuning.ll
@@ -83,7 +83,7 @@ L2:
 
 ; CHECK-LABEL: test_add_tbz:
 ; CHECK: adds
-; CHECK: b.ge
+; CHECK: b.pl
 ; CHECK: ret
 define void @test_add_tbz(i32 %a, i32 %b, i32* %ptr) {
 entry:
@@ -99,7 +99,7 @@ L2:
 
 ; CHECK-LABEL: test_subs_tbz:
 ; CHECK: subs
-; CHECK: b.ge
+; CHECK: b.pl
 ; CHECK: ret
 define void @test_subs_tbz(i32 %a, i32 %b, i32* %ptr) {
 entry:
@@ -115,7 +115,7 @@ L2:
 
 ; CHECK-LABEL: test_add_tbnz
 ; CHECK: adds
-; CHECK: b.lt
+; CHECK: b.mi
 ; CHECK: ret
 define void @test_add_tbnz(i32 %a, i32 %b, i32* %ptr) {
 entry:
@@ -131,7 +131,7 @@ L2:
 
 ; CHECK-LABEL: test_subs_tbnz
 ; CHECK: subs
-; CHECK: b.lt
+; CHECK: b.mi
 ; CHECK: ret
 define void @test_subs_tbnz(i32 %a, i32 %b, i32* %ptr) {
 entry: