From: Matt Arsenault Date: Sat, 21 Sep 2019 02:37:33 +0000 (+0000) Subject: AMDGPU/GlobalISel: Allow selection of scalar min/max X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f9dc386cbe0b863ae77f8597b336d4672579e54e;p=llvm AMDGPU/GlobalISel: Allow selection of scalar min/max I believe all of the uniform/divergent pattern predicates are redundant and can be removed. The uniformity bit already influences the register class, and nothhing has broken when I've removed this and others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372450 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AMDGPU/SOPInstructions.td b/lib/Target/AMDGPU/SOPInstructions.td index 2cd4e1cbc07..d31a49f428e 100644 --- a/lib/Target/AMDGPU/SOPInstructions.td +++ b/lib/Target/AMDGPU/SOPInstructions.td @@ -419,16 +419,16 @@ def S_SUBB_U32 : SOP2_32 <"s_subb_u32", let isCommutable = 1 in { def S_MIN_I32 : SOP2_32 <"s_min_i32", - [(set i32:$sdst, (UniformBinFrag i32:$src0, i32:$src1))] + [(set i32:$sdst, (smin i32:$src0, i32:$src1))] >; def S_MIN_U32 : SOP2_32 <"s_min_u32", - [(set i32:$sdst, (UniformBinFrag i32:$src0, i32:$src1))] + [(set i32:$sdst, (umin i32:$src0, i32:$src1))] >; def S_MAX_I32 : SOP2_32 <"s_max_i32", - [(set i32:$sdst, (UniformBinFrag i32:$src0, i32:$src1))] + [(set i32:$sdst, (smax i32:$src0, i32:$src1))] >; def S_MAX_U32 : SOP2_32 <"s_max_u32", - [(set i32:$sdst, (UniformBinFrag i32:$src0, i32:$src1))] + [(set i32:$sdst, (umax i32:$src0, i32:$src1))] >; } // End isCommutable = 1 } // End Defs = [SCC] diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir index 50811a47cd2..1ffe7d3d679 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir @@ -1,10 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s -# RUN: FileCheck -check-prefix=ERR %s < %t - -# ERR-NOT: remark: -# ERR: remark: :0:0: cannot select: %2:sgpr(s32) = G_SMAX %0:sgpr, %1:sgpr (in function: smax_s32_ss) -# ERR-NOT: remark: +# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s --- name: smax_s32_ss @@ -15,10 +10,10 @@ body: | bb.0: liveins: $sgpr0, $sgpr1 ; GCN-LABEL: name: smax_s32_ss - ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GCN: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[COPY1]] - ; GCN: S_ENDPGM 0, implicit [[SMAX]](s32) + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GCN: [[S_MAX_I32_:%[0-9]+]]:sreg_32 = S_MAX_I32 [[COPY]], [[COPY1]], implicit-def $scc + ; GCN: S_ENDPGM 0, implicit [[S_MAX_I32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr1 %2:sgpr(s32) = G_SMAX %0, %1 diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir index 39fd79660f7..3c37a9425d4 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir @@ -1,10 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s -# RUN: FileCheck -check-prefix=ERR %s < %t - -# ERR-NOT: remark: -# ERR: remark: :0:0: cannot select: %2:sgpr(s32) = G_SMIN %0:sgpr, %1:sgpr (in function: smin_s32_ss) -# ERR-NOT: remark: +# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s --- name: smin_s32_ss @@ -15,10 +10,10 @@ body: | bb.0: liveins: $sgpr0, $sgpr1 ; GCN-LABEL: name: smin_s32_ss - ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GCN: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[COPY]], [[COPY1]] - ; GCN: S_ENDPGM 0, implicit [[SMIN]](s32) + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GCN: [[S_MIN_I32_:%[0-9]+]]:sreg_32 = S_MIN_I32 [[COPY]], [[COPY1]], implicit-def $scc + ; GCN: S_ENDPGM 0, implicit [[S_MIN_I32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr1 %2:sgpr(s32) = G_SMIN %0, %1 diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir index d4537a07c4d..a5ae6ab6ca8 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir @@ -1,10 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s -# RUN: FileCheck -check-prefix=ERR %s < %t - -# ERR-NOT: remark: -# ERR: remark: :0:0: cannot select: %2:sgpr(s32) = G_UMAX %0:sgpr, %1:sgpr (in function: umax_s32_ss) -# ERR-NOT: remark: +# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s --- name: umax_s32_ss @@ -15,10 +10,10 @@ body: | bb.0: liveins: $sgpr0, $sgpr1 ; GCN-LABEL: name: umax_s32_ss - ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GCN: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[COPY]], [[COPY1]] - ; GCN: S_ENDPGM 0, implicit [[UMAX]](s32) + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GCN: [[S_MAX_U32_:%[0-9]+]]:sreg_32 = S_MAX_U32 [[COPY]], [[COPY1]], implicit-def $scc + ; GCN: S_ENDPGM 0, implicit [[S_MAX_U32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr1 %2:sgpr(s32) = G_UMAX %0, %1 diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir index cfa573c9fca..be097fc126d 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir @@ -1,10 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s -# RUN: FileCheck -check-prefix=ERR %s < %t - -# ERR-NOT: remark: -# ERR: remark: :0:0: cannot select: %2:sgpr(s32) = G_UMIN %0:sgpr, %1:sgpr (in function: umin_s32_ss) -# ERR-NOT: remark: +# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s --- name: umin_s32_ss @@ -15,10 +10,10 @@ body: | bb.0: liveins: $sgpr0, $sgpr1 ; GCN-LABEL: name: umin_s32_ss - ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GCN: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[COPY]], [[COPY1]] - ; GCN: S_ENDPGM 0, implicit [[UMIN]](s32) + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GCN: [[S_MIN_U32_:%[0-9]+]]:sreg_32 = S_MIN_U32 [[COPY]], [[COPY1]], implicit-def $scc + ; GCN: S_ENDPGM 0, implicit [[S_MIN_U32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr1 %2:sgpr(s32) = G_UMIN %0, %1