From: Sjoerd Meijer <sjoerd.meijer@arm.com>
Date: Fri, 13 Jul 2018 15:25:42 +0000 (+0000)
Subject: [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions (cont'd)
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f907c503aba30873a8edf32759408a26ddcd3b62;p=llvm

[AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions (cont'd)

Follow up of rL336913: fix base class description. Thanks to Ahmed Bougacha
for pointing this out.

Differential Revision: https://reviews.llvm.org/D49284


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337009 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index 111dbf3810b..1ba2f38f67e 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -3406,8 +3406,8 @@ class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
 }
 
 // Armv8.4 LDAPR & STLR with Immediate Offset instruction
-multiclass BaseLoadStoreUnscaleV84<string asm, bits<2> sz, bits<2> opc,
-                                   RegisterOperand regtype > {
+multiclass BaseLoadUnscaleV84<string asm, bits<2> sz, bits<2> opc,
+                              RegisterOperand regtype > {
   def i : BaseLoadStoreUnscale<sz, 0, opc, (outs regtype:$Rt),
                                (ins GPR64sp:$Rn, simm9:$offset), asm, []>,
           Sched<[WriteST]> {
@@ -3418,6 +3418,19 @@ multiclass BaseLoadStoreUnscaleV84<string asm, bits<2> sz, bits<2> opc,
                   (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
 }
 
+multiclass BaseStoreUnscaleV84<string asm, bits<2> sz, bits<2> opc,
+                               RegisterOperand regtype > {
+  def i : BaseLoadStoreUnscale<sz, 0, opc, (outs),
+                               (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
+                               asm, []>,
+          Sched<[WriteST]> {
+    let Inst{29} = 0;
+    let Inst{24} = 1;
+  }
+  def : InstAlias<asm # "\t$Rt, [$Rn]",
+                  (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
+}
+
 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype,
                    string asm, list<dag> pattern> {
   let AddedComplexity = 1 in // try this before LoadUI
diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index e5ab8044598..6ea7b01e517 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2434,19 +2434,19 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",
 
 // Armv8.4 LDAPR & STLR with Immediate Offset instruction
 let Predicates = [HasV8_4a] in {
-defm STLURB     : BaseLoadStoreUnscaleV84<"stlurb",   0b00, 0b00, GPR32>;
-defm STLURH     : BaseLoadStoreUnscaleV84<"stlurh",   0b01, 0b00, GPR32>;
-defm STLUR      : BaseLoadStoreUnscaleV84<"stlur",    0b10, 0b00, GPR32>;
-defm STLUR64    : BaseLoadStoreUnscaleV84<"stlur",    0b11, 0b00, GPR64>;
-defm LDAPURB    : BaseLoadStoreUnscaleV84<"ldapurb",  0b00, 0b01, GPR32>;
-defm LDAPURSB   : BaseLoadStoreUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;
-defm LDAPURSB64 : BaseLoadStoreUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>;
-defm LDAPURH    : BaseLoadStoreUnscaleV84<"ldapurh",  0b01, 0b01, GPR32>;
-defm LDAPURSH   : BaseLoadStoreUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;
-defm LDAPURSH64 : BaseLoadStoreUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>;
-defm LDAPUR     : BaseLoadStoreUnscaleV84<"ldapur",   0b10, 0b01, GPR32>;
-defm LDAPURSW   : BaseLoadStoreUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>;
-defm LDAPUR64   : BaseLoadStoreUnscaleV84<"ldapur",   0b11, 0b01, GPR64>;
+defm STLURB     : BaseStoreUnscaleV84<"stlurb",  0b00, 0b00, GPR32>;
+defm STLURH     : BaseStoreUnscaleV84<"stlurh",  0b01, 0b00, GPR32>;
+defm STLURW     : BaseStoreUnscaleV84<"stlur",   0b10, 0b00, GPR32>;
+defm STLURX     : BaseStoreUnscaleV84<"stlur",   0b11, 0b00, GPR64>;
+defm LDAPURB    : BaseLoadUnscaleV84<"ldapurb",  0b00, 0b01, GPR32>;
+defm LDAPURSBW  : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>;
+defm LDAPURSBX  : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>;
+defm LDAPURH    : BaseLoadUnscaleV84<"ldapurh",  0b01, 0b01, GPR32>;
+defm LDAPURSHW  : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>;
+defm LDAPURSHX  : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>;
+defm LDAPUR     : BaseLoadUnscaleV84<"ldapur",   0b10, 0b01, GPR32>;
+defm LDAPURSW   : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>;
+defm LDAPURX    : BaseLoadUnscaleV84<"ldapur",   0b11, 0b01, GPR64>;
 }
 
 // Match all store 64 bits width whose type is compatible with FPR64
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index ff3e0ca8dc6..cef0ff34644 100644
--- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -1185,11 +1185,11 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
   case AArch64::LDRWpost:
   case AArch64::STLURBi:
   case AArch64::STLURHi:
-  case AArch64::STLURi:
+  case AArch64::STLURWi:
   case AArch64::LDAPURBi:
-  case AArch64::LDAPURSBi:
+  case AArch64::LDAPURSBWi:
   case AArch64::LDAPURHi:
-  case AArch64::LDAPURSHi:
+  case AArch64::LDAPURSHWi:
   case AArch64::LDAPURi:
     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
     break;
@@ -1214,10 +1214,10 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
   case AArch64::LDRSWpost:
   case AArch64::LDRXpost:
   case AArch64::LDAPURSWi:
-  case AArch64::LDAPURSH64i:
-  case AArch64::LDAPURSB64i:
-  case AArch64::STLUR64i:
-  case AArch64::LDAPUR64i:
+  case AArch64::LDAPURSHXi:
+  case AArch64::LDAPURSBXi:
+  case AArch64::STLURXi:
+  case AArch64::LDAPURXi:
     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
     break;
   case AArch64::LDURQi: