From: Hiroshi Inoue <inouehrs@jp.ibm.com>
Date: Wed, 18 Jul 2018 06:04:43 +0000 (+0000)
Subject: [NFC] fix trivial typos in comments
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f8f02e122b852694517aba17c33818584fc98999;p=llvm

[NFC] fix trivial typos in comments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337351 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/PPCExpandISEL.cpp b/lib/Target/PowerPC/PPCExpandISEL.cpp
index a8b6b611620..fe41e1b36a5 100644
--- a/lib/Target/PowerPC/PPCExpandISEL.cpp
+++ b/lib/Target/PowerPC/PPCExpandISEL.cpp
@@ -285,7 +285,7 @@ void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
 
     // Special case 1, all registers used by ISEL are the same one.
     if (!IsADDIInstRequired && !IsORIInstRequired) {
-      LLVM_DEBUG(dbgs() << "Remove redudant ISEL instruction.");
+      LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction.");
       // FIXME: if the CR field used has no other uses, we could eliminate the
       // instruction that defines it. This would have to be done manually
       // since this pass runs too late to run DCE after it.
@@ -305,7 +305,7 @@ void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
     // thereby preventing this ISEL from being folded.
     if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {
       LLVM_DEBUG(
-          dbgs() << "Fold the ISEL instruction to an unconditonal copy.");
+          dbgs() << "Fold the ISEL instruction to an unconditional copy.");
       NumFolded++;
       // Note: we're using both the TrueValue and FalseValue operands so as
       // not to lose the kill flag if it is set on either of them.
diff --git a/lib/Target/PowerPC/PPCReduceCRLogicals.cpp b/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
index 9c2350f0f2f..173fc18b9eb 100644
--- a/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
+++ b/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
@@ -67,7 +67,7 @@ static void updatePHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB,
     for (unsigned i = 2, e = MI.getNumOperands() + 1; i != e; i += 2) {
       MachineOperand &MO = MI.getOperand(i);
       if (MO.getMBB() == OrigMBB) {
-        // Check if the instruction is actualy defined in NewMBB.
+        // Check if the instruction is actually defined in NewMBB.
         if (MI.getOperand(i - 1).isReg()) {
           MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(i - 1).getReg());
           if (DefMI->getParent() == NewMBB ||
@@ -152,7 +152,7 @@ static bool splitMBB(BlockSplitInfo &BSI) {
   if (ThisMBB->succ_size() != 2) {
     LLVM_DEBUG(
         dbgs() << "Don't know how to handle blocks that don't have exactly"
-               << " two succesors.\n");
+               << " two successors.\n");
     return false;
   }