From: Alex Bradbury <asb@lowrisc.org>
Date: Tue, 8 Aug 2017 14:32:35 +0000 (+0000)
Subject: [RISCV] Add basic RISCVAsmParser
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f86950695523da883812cd69781f754928aa9b02;p=llvm

[RISCV] Add basic RISCVAsmParser

This doesn't yet support parsing things like %pcrel_hi(foo), but will handle
basic instructions with register or immediate operands.

Differential Revision: https://reviews.llvm.org/D23563


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310361 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/RISCV/CMakeLists.txt b/lib/Target/RISCV/CMakeLists.txt
index c8887548b91..47e53a36722 100644
--- a/lib/Target/RISCV/CMakeLists.txt
+++ b/lib/Target/RISCV/CMakeLists.txt
@@ -3,6 +3,7 @@ set(LLVM_TARGET_DEFINITIONS RISCV.td)
 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
+tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 
@@ -10,5 +11,6 @@ add_llvm_target(RISCVCodeGen
   RISCVTargetMachine.cpp
   )
 
+add_subdirectory(AsmParser)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)
diff --git a/lib/Target/RISCV/LLVMBuild.txt b/lib/Target/RISCV/LLVMBuild.txt
index 9ba5fec928f..3e540048921 100644
--- a/lib/Target/RISCV/LLVMBuild.txt
+++ b/lib/Target/RISCV/LLVMBuild.txt
@@ -16,12 +16,13 @@
 ;===------------------------------------------------------------------------===;
 
 [common]
-subdirectories = TargetInfo MCTargetDesc
+subdirectories = AsmParser TargetInfo MCTargetDesc
 
 [component_0]
 type = TargetGroup
 name = RISCV
 parent = Target
+has_asmparser = 1
 
 [component_1]
 type = Library
diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td
index 14838309a1b..19e11839ac3 100644
--- a/lib/Target/RISCV/RISCV.td
+++ b/lib/Target/RISCV/RISCV.td
@@ -22,6 +22,11 @@ def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
+def RISCVAsmParser : AsmParser {
+  let ShouldEmitMatchRegisterAltName = 1;
+}
+
 def RISCV : Target {
   let InstructionSet = RISCVInstrInfo;
+  let AssemblyParsers = [RISCVAsmParser];
 }
diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td
index 52530c2f136..93d13f79390 100644
--- a/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/lib/Target/RISCV/RISCVInstrInfo.td
@@ -13,7 +13,16 @@
 
 include "RISCVInstrFormats.td"
 
-def simm12 : Operand<i32>;
+class SImmAsmOperand<int width>
+  : AsmOperandClass {
+  let Name = "SImm" # width;
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = !strconcat("Invalid", Name);
+}
+
+def simm12 : Operand<i32> {
+  let ParserMatchClass = SImmAsmOperand<12>;
+}
 
 // As noted in RISCVRegisterInfo.td, the hope is that support for
 // variable-sized register classes will mean that instruction definitions do