From: Artyom Skrobov <Artyom.Skrobov@arm.com>
Date: Wed, 15 Mar 2017 10:19:16 +0000 (+0000)
Subject: [Thumb1] Fix the bug when adding/subtracting -2147483648
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f803e21e4f245453fc3d0cbfac4d2e0fd4d0f7bb;p=llvm

[Thumb1] Fix the bug when adding/subtracting -2147483648

Differential Revision: https://reviews.llvm.org/D30829

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297820 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 15ae0c7940b..a13ef5820bf 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -9788,8 +9788,8 @@ static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG,
   if (Subtarget->isThumb1Only()) {
     SDValue RHS = N->getOperand(1);
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
-      int64_t imm = C->getSExtValue();
-      if (imm < 0) {
+      int32_t imm = C->getSExtValue();
+      if (-imm > 0) {
         SDLoc DL(N);
         RHS = DAG.getConstant(-imm, DL, MVT::i32);
         unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
@@ -9806,8 +9806,8 @@ static SDValue PerformAddeSubeCombine(SDNode *N, SelectionDAG &DAG,
   if (Subtarget->isThumb1Only()) {
     SDValue RHS = N->getOperand(1);
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
-      int64_t imm = C->getSExtValue();
-      if (imm < 0) {
+      int32_t imm = C->getSExtValue();
+      if (-imm > 0) {
         SDLoc DL(N);
 
         // The with-carry-in form matches bitwise not instead of the negation.
diff --git a/test/CodeGen/Thumb/long.ll b/test/CodeGen/Thumb/long.ll
index e35f7cc82b1..c549bd425aa 100644
--- a/test/CodeGen/Thumb/long.ll
+++ b/test/CodeGen/Thumb/long.ll
@@ -194,3 +194,15 @@ entry:
 ; CHECK: movs r1, r3
 }
 
+; "sub 2147483648" has to be lowered into "add -2147483648"
+define i64 @f12(i64 %x, i64 %y) {
+entry:
+        %tmp1 = sub i64 %x, 2147483648
+        ret i64 %tmp1
+; CHECK-LABEL: f12:
+; CHECK: movs r2, #1
+; CHECK: lsls r2, r2, #31
+; CHECK: movs r3, #0
+; CHECK: adds r0, r0, r2
+; CHECK: sbcs r1, r3
+}