From: Simon Pilgrim Date: Wed, 26 Dec 2018 12:09:10 +0000 (+0000) Subject: [AMDGPU] Regenerate i64 shift tests. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f77e034b28f6326018b1f400649c55b88ebb1d6e;p=llvm [AMDGPU] Regenerate i64 shift tests. To show codegen diff due to a future SimplifyDemandedBits patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350065 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/AMDGPU/lshl64-to-32.ll b/test/CodeGen/AMDGPU/lshl64-to-32.ll index b7e5eab275c..1735dec2d22 100644 --- a/test/CodeGen/AMDGPU/lshl64-to-32.ll +++ b/test/CodeGen/AMDGPU/lshl64-to-32.ll @@ -1,9 +1,19 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; GCN-LABEL: {{^}}zext_shl64_to_32: -; GCN: s_lshl_b32 -; GCN-NOT: s_lshl_b64 define amdgpu_kernel void @zext_shl64_to_32(i64 addrspace(1)* nocapture %out, i32 %x) { +; GCN-LABEL: zext_shl64_to_32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s4, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s4, s4, 2 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm %and = and i32 %x, 1073741823 %ext = zext i32 %and to i64 %shl = shl i64 %ext, 2 @@ -11,10 +21,20 @@ define amdgpu_kernel void @zext_shl64_to_32(i64 addrspace(1)* nocapture %out, i3 ret void } -; GCN-LABEL: {{^}}sext_shl64_to_32: -; GCN: s_lshl_b32 -; GCN-NOT: s_lshl_b64 define amdgpu_kernel void @sext_shl64_to_32(i64 addrspace(1)* nocapture %out, i32 %x) { +; GCN-LABEL: sext_shl64_to_32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s4, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s4, s4, 0x1fffffff +; GCN-NEXT: s_lshl_b32 s4, s4, 2 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm %and = and i32 %x, 536870911 %ext = sext i32 %and to i64 %shl = shl i64 %ext, 2 @@ -22,10 +42,21 @@ define amdgpu_kernel void @sext_shl64_to_32(i64 addrspace(1)* nocapture %out, i3 ret void } -; GCN-LABEL: {{^}}zext_shl64_overflow: -; GCN: s_lshl_b64 -; GCN-NOT: s_lshl_b32 define amdgpu_kernel void @zext_shl64_overflow(i64 addrspace(1)* nocapture %out, i32 %x) { +; GCN-LABEL: zext_shl64_overflow: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s2, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s5, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s4, s2, 0x7fffffff +; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 2 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm %and = and i32 %x, 2147483647 %ext = zext i32 %and to i64 %shl = shl i64 %ext, 2 @@ -33,10 +64,21 @@ define amdgpu_kernel void @zext_shl64_overflow(i64 addrspace(1)* nocapture %out, ret void } -; GCN-LABEL: {{^}}sext_shl64_overflow: -; GCN: s_lshl_b64 -; GCN-NOT: s_lshl_b32 define amdgpu_kernel void @sext_shl64_overflow(i64 addrspace(1)* nocapture %out, i32 %x) { +; GCN-LABEL: sext_shl64_overflow: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s2, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s5, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s4, s2, 0x7fffffff +; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 2 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm %and = and i32 %x, 2147483647 %ext = sext i32 %and to i64 %shl = shl i64 %ext, 2 @@ -44,10 +86,19 @@ define amdgpu_kernel void @sext_shl64_overflow(i64 addrspace(1)* nocapture %out, ret void } -; GCN-LABEL: {{^}}mulu24_shl64: -; GCN: v_mul_u32_u24_e32 [[M:v[0-9]+]], 7, v{{[0-9]+}} -; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, 2, [[M]] define amdgpu_kernel void @mulu24_shl64(i32 addrspace(1)* nocapture %arg) { +; GCN-LABEL: mulu24_shl64: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: v_and_b32_e32 v0, 6, v0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: v_mul_u32_u24_e32 v0, 7, v0 +; GCN-NEXT: s_mov_b32 s2, 0 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v1, v[0:1], s[0:3], 0 addr64 +; GCN-NEXT: s_endpgm bb: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = and i32 %tmp, 6 @@ -58,10 +109,26 @@ bb: ret void } -; GCN-LABEL: {{^}}muli24_shl64: -; GCN: v_mul_i32_i24_e32 [[M:v[0-9]+]], -7, v{{[0-9]+}} -; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, 3, [[M]] define amdgpu_kernel void @muli24_shl64(i64 addrspace(1)* nocapture %arg, i32 addrspace(1)* nocapture readonly %arg1) { +; GCN-LABEL: muli24_shl64: +; GCN: ; %bb.0: ; %bb +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0 +; GCN-NEXT: v_mov_b32_e32 v2, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b64 s[4:5], s[2:3] +; GCN-NEXT: buffer_load_dword v1, v[1:2], s[4:7], 0 addr64 +; GCN-NEXT: s_mov_b64 s[2:3], s[6:7] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_or_b32_e32 v1, 0x800000, v1 +; GCN-NEXT: v_mul_i32_i24_e32 v1, -7, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 3, v0 +; GCN-NEXT: v_mov_b32_e32 v4, v2 +; GCN-NEXT: buffer_store_dwordx2 v[1:2], v[3:4], s[0:3], 0 addr64 +; GCN-NEXT: s_endpgm bb: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = sext i32 %tmp to i64