From: Konstantin Zhuravlyov <kzhuravl_dev@outlook.com>
Date: Mon, 20 Mar 2017 18:06:45 +0000 (+0000)
Subject: [AMDGPU] Run always inliner early in opt
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f6fa4ce469b08f36f67ecc136aef9afca7ae9b24;p=llvm

[AMDGPU] Run always inliner early in opt

Differential Revision: https://reviews.llvm.org/D31141


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298281 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 914217af73b..1b25eb4fe3b 100644
--- a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -252,6 +252,7 @@ void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
           return !GV.use_empty();
         }));
         PM.add(createGlobalDCEPass());
+        PM.add(createAMDGPUAlwaysInlinePass());
       }
   });
 }
diff --git a/test/CodeGen/AMDGPU/early-inline-alias.ll b/test/CodeGen/AMDGPU/early-inline-alias.ll
new file mode 100644
index 00000000000..42dfa4e7ab4
--- /dev/null
+++ b/test/CodeGen/AMDGPU/early-inline-alias.ll
@@ -0,0 +1,12 @@
+; RUN: opt -mtriple=amdgcn-- -O1 -S -inline-threshold=1 %s | FileCheck %s
+
+; CHECK: @add1alias = alias i32 (i32), i32 (i32)* @add1
+; CHECK: @add1alias2 = alias i32 (i32), i32 (i32)* @add1
+
+@add1alias = alias i32 (i32), i32 (i32)* @add1
+@add1alias2 = alias i32 (i32), i32 (i32)* @add1
+
+define i32 @add1(i32) {
+  %2 = add nsw i32 %0, 1
+  ret i32 %2
+}
diff --git a/test/CodeGen/AMDGPU/early-inline.ll b/test/CodeGen/AMDGPU/early-inline.ll
new file mode 100644
index 00000000000..8395ad818ab
--- /dev/null
+++ b/test/CodeGen/AMDGPU/early-inline.ll
@@ -0,0 +1,21 @@
+; RUN: opt -mtriple=amdgcn-- -O1 -S -inline-threshold=1 -amdgpu-internalize-symbols %s | FileCheck %s
+
+define i32 @callee(i32 %x) {
+entry:
+  %mul1 = mul i32 %x, %x
+  %mul2 = mul i32 %mul1, %x
+  %mul3 = mul i32 %mul1, %mul2
+  %mul4 = mul i32 %mul3, %mul2
+  %mul5 = mul i32 %mul4, %mul3
+  ret i32 %mul5
+}
+
+; CHECK-LABEL: @caller
+; CHECK: mul i32
+; CHECK-NOT: call i32
+
+define amdgpu_kernel i32 @caller(i32 %x) {
+entry:
+  %res = call i32 @callee(i32 %x)
+  ret i32 %res
+}