From: Sanjay Patel Date: Sun, 15 Jan 2017 16:38:19 +0000 (+0000) Subject: [InstCombine] use m_APInt to allow ashr folds for vectors with splat constants X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f6be6abb8180ed160a2c8380082e83021c0751ef;p=llvm [InstCombine] use m_APInt to allow ashr folds for vectors with splat constants git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292064 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Transforms/InstCombine/InstCombineShifts.cpp b/lib/Transforms/InstCombine/InstCombineShifts.cpp index f74e499397e..8453152a448 100644 --- a/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -814,11 +814,12 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) { return R; unsigned BitWidth = I.getType()->getScalarSizeInBits(); - if (ConstantInt *Op1C = dyn_cast(Op1)) { - unsigned ShAmt = Op1C->getZExtValue(); + const APInt *ShAmtAPInt; + if (match(Op1, m_APInt(ShAmtAPInt))) { + unsigned ShAmt = ShAmtAPInt->getZExtValue(); // If the shift amount equals the difference in width of the destination - // and source types: + // and source scalar types: // ashr (shl (zext X), C), C --> sext X Value *X; if (match(Op0, m_Shl(m_ZExt(m_Value(X)), m_Specific(Op1))) && diff --git a/test/Transforms/InstCombine/exact.ll b/test/Transforms/InstCombine/exact.ll index 436d5081c7a..96b6fd68996 100644 --- a/test/Transforms/InstCombine/exact.ll +++ b/test/Transforms/InstCombine/exact.ll @@ -99,12 +99,12 @@ define i64 @ashr1(i64 %X) { ret i64 %B } -; FIXME: The ashr should be exact (like it is in the preceding test). +; The vector ashr should be exact (like it is in the preceding test). define <2 x i64> @ashr1_vec(<2 x i64> %X) { ; CHECK-LABEL: @ashr1_vec( ; CHECK-NEXT: [[A:%.*]] = shl <2 x i64> %X, -; CHECK-NEXT: [[B:%.*]] = ashr <2 x i64> [[A]], +; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i64> [[A]], ; CHECK-NEXT: ret <2 x i64> [[B]] ; %A = shl <2 x i64> %X, diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index 7fef649348c..e3f00f6cb87 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -1183,12 +1183,11 @@ define i1 @icmp_sext8trunc(i32 %x) { ret i1 %cmp } -; FIXME: Vectors should fold the same way. +; Vectors should fold the same way. define <2 x i1> @icmp_sext8trunc_vec(<2 x i32> %x) { ; CHECK-LABEL: @icmp_sext8trunc_vec( -; CHECK-NEXT: [[SEXT1:%.*]] = shl <2 x i32> %x, -; CHECK-NEXT: [[SEXT:%.*]] = ashr <2 x i32> [[SEXT:%.*]]1, -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[SEXT]], +; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> %x to <2 x i8> +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %trunc = trunc <2 x i32> %x to <2 x i8> diff --git a/test/Transforms/InstCombine/pr17827.ll b/test/Transforms/InstCombine/pr17827.ll index a3ed5e1697e..ada6edab69c 100644 --- a/test/Transforms/InstCombine/pr17827.ll +++ b/test/Transforms/InstCombine/pr17827.ll @@ -48,14 +48,14 @@ define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) { } ; FIXME: Vectors should fold the same way. + define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) { ; CHECK-LABEL: @test_shift_and_cmp_changed1_vec( ; CHECK-NEXT: [[ANDP:%.*]] = and <2 x i8> %p, ; CHECK-NEXT: [[ANDQ:%.*]] = and <2 x i8> %q, ; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[ANDQ]], [[ANDP]] ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[OR]], -; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i8> [[SHL]], -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[ASHR]], +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[SHL]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %andp = and <2 x i8> %p, diff --git a/test/Transforms/InstCombine/select-bitext.ll b/test/Transforms/InstCombine/select-bitext.ll index 6e374f5221d..b66a9eef4ab 100644 --- a/test/Transforms/InstCombine/select-bitext.ll +++ b/test/Transforms/InstCombine/select-bitext.ll @@ -100,7 +100,7 @@ define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) { ; CHECK-LABEL: @trunc_sel_larger_sext_vec( ; CHECK-NEXT: [[TRUNC:%.*]] = zext <2 x i32> %a to <2 x i64> ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[TRUNC]], -; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[SEXT]], +; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i64> [[SEXT]], ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP1]], <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[EXT]] ; @@ -127,7 +127,7 @@ define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) { ; CHECK-LABEL: @trunc_sel_smaller_sext_vec( ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32> ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[TRUNC]], -; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], +; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i32> [[SEXT]], ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[EXT]] ; @@ -153,7 +153,7 @@ define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) { define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) { ; CHECK-LABEL: @trunc_sel_equal_sext_vec( ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> %a, -; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], +; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i32> [[SEXT]], ; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[EXT]] ; diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll index 5f59ab8ffdc..98356cbe2aa 100644 --- a/test/Transforms/InstCombine/shift.ll +++ b/test/Transforms/InstCombine/shift.ll @@ -1046,7 +1046,7 @@ define <2 x i65> @test_63(<2 x i64> %t) { ; CHECK-LABEL: @test_63( ; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> %t to <2 x i65> ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], -; CHECK-NEXT: [[B:%.*]] = ashr <2 x i65> [[SEXT]], +; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i65> [[SEXT]], ; CHECK-NEXT: ret <2 x i65> [[B]] ; %a = zext <2 x i64> %t to <2 x i65> diff --git a/test/Transforms/InstCombine/signext.ll b/test/Transforms/InstCombine/signext.ll index fea485d8e7e..ff92ec0a8e3 100644 --- a/test/Transforms/InstCombine/signext.ll +++ b/test/Transforms/InstCombine/signext.ll @@ -76,13 +76,11 @@ define i32 @test6(i16 %P) { ret i32 %tmp.5 } -; FIXME: Vectors should get the same fold as above. +; Vectors should get the same fold as above. define <2 x i32> @test6_splat_vec(<2 x i12> %P) { ; CHECK-LABEL: @test6_splat_vec( -; CHECK-NEXT: [[Z:%.*]] = zext <2 x i12> %P to <2 x i32> -; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i32> [[Z]], -; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[SHL]], +; CHECK-NEXT: [[ASHR:%.*]] = sext <2 x i12> %P to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[ASHR]] ; %z = zext <2 x i12> %P to <2 x i32> diff --git a/test/Transforms/InstCombine/vector-casts.ll b/test/Transforms/InstCombine/vector-casts.ll index 8d01cad4b45..0848a6e8742 100644 --- a/test/Transforms/InstCombine/vector-casts.ll +++ b/test/Transforms/InstCombine/vector-casts.ll @@ -110,23 +110,11 @@ define <2 x i64> @bar(<2 x i65> %t) { ret <2 x i64> %b } -define <2 x i65> @foos(<2 x i64> %t) { -; CHECK-LABEL: @foos( -; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> %t to <2 x i65> -; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], -; CHECK-NEXT: [[B:%.*]] = ashr <2 x i65> [[SEXT]], -; CHECK-NEXT: ret <2 x i65> [[B]] -; - %a = trunc <2 x i64> %t to <2 x i32> - %b = sext <2 x i32> %a to <2 x i65> - ret <2 x i65> %b -} - define <2 x i64> @bars(<2 x i65> %t) { ; CHECK-LABEL: @bars( ; CHECK-NEXT: [[A:%.*]] = trunc <2 x i65> %t to <2 x i64> ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[A]], -; CHECK-NEXT: [[B:%.*]] = ashr <2 x i64> [[SEXT]], +; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i64> [[SEXT]], ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = trunc <2 x i65> %t to <2 x i32> @@ -137,7 +125,7 @@ define <2 x i64> @bars(<2 x i65> %t) { define <2 x i64> @quxs(<2 x i64> %t) { ; CHECK-LABEL: @quxs( ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> %t, -; CHECK-NEXT: [[B:%.*]] = ashr <2 x i64> [[SEXT]], +; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i64> [[SEXT]], ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = trunc <2 x i64> %t to <2 x i32> @@ -148,7 +136,7 @@ define <2 x i64> @quxs(<2 x i64> %t) { define <2 x i64> @quxt(<2 x i64> %t) { ; CHECK-LABEL: @quxt( ; CHECK-NEXT: [[A:%.*]] = shl <2 x i64> %t, -; CHECK-NEXT: [[B:%.*]] = ashr <2 x i64> [[A]], +; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i64> [[A]], ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = shl <2 x i64> %t,