From: Luqman Aden <me@luqman.ca>
Date: Sun, 31 Mar 2019 08:58:50 +0000 (+0000)
Subject: [NFC][InstCombine] Add tests for combining icmp of no-wrap sub w/ constant.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f57a892ba8206d7d66030707d35173512d5e541a;p=llvm

[NFC][InstCombine] Add tests for combining icmp of no-wrap sub w/ constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357360 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/Transforms/InstCombine/icmp-sub.ll b/test/Transforms/InstCombine/icmp-sub.ll
new file mode 100644
index 00000000000..e9fbec9068d
--- /dev/null
+++ b/test/Transforms/InstCombine/icmp-sub.ll
@@ -0,0 +1,90 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i1 @test_nuw_and_unsigned_pred(i64 %x) {
+; CHECK-LABEL: @test_nuw_and_unsigned_pred(
+; CHECK-NEXT:    [[Y:%.*]] = sub nuw i64 10, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp ult i64 [[Y]], 3
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nuw i64 10, %x
+  %z = icmp ult i64 %y, 3
+  ret i1 %z
+}
+
+define i1 @test_nsw_and_signed_pred(i64 %x) {
+; CHECK-LABEL: @test_nsw_and_signed_pred(
+; CHECK-NEXT:    [[Y:%.*]] = sub nsw i64 3, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp sgt i64 [[Y]], 10
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nsw i64 3, %x
+  %z = icmp sgt i64 %y, 10
+  ret i1 %z
+}
+
+define i1 @test_nuw_nsw_and_unsigned_pred(i64 %x) {
+; CHECK-LABEL: @test_nuw_nsw_and_unsigned_pred(
+; CHECK-NEXT:    [[Y:%.*]] = sub nuw nsw i64 10, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp ult i64 [[Y]], 4
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nuw nsw i64 10, %x
+  %z = icmp ule i64 %y, 3
+  ret i1 %z
+}
+
+define i1 @test_nuw_nsw_and_signed_pred(i64 %x) {
+; CHECK-LABEL: @test_nuw_nsw_and_signed_pred(
+; CHECK-NEXT:    [[Y:%.*]] = sub nuw nsw i64 10, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp slt i64 [[Y]], 3
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nuw nsw i64 10, %x
+  %z = icmp slt i64 %y, 3
+  ret i1 %z
+}
+
+define i1 @test_negative_nuw_and_signed_pred(i64 %x) {
+; CHECK-LABEL: @test_negative_nuw_and_signed_pred(
+; CHECK-NEXT:    [[Y:%.*]] = sub nuw i64 10, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp slt i64 [[Y]], 3
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nuw i64 10, %x
+  %z = icmp slt i64 %y, 3
+  ret i1 %z
+}
+
+define i1 @test_negative_nsw_and_unsigned_pred(i64 %x) {
+; CHECK-LABEL: @test_negative_nsw_and_unsigned_pred(
+; CHECK-NEXT:    [[Y:%.*]] = sub nsw i64 10, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp ult i64 [[Y]], 3
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nsw i64 10, %x
+  %z = icmp ult i64 %y, 3
+  ret i1 %z
+}
+
+define i1 @test_negative_combined_sub_unsigned_overflow(i64 %x) {
+; CHECK-LABEL: @test_negative_combined_sub_unsigned_overflow(
+; CHECK-NEXT:    [[Y:%.*]] = sub nuw i64 10, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp ult i64 [[Y]], 11
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nuw i64 10, %x
+  %z = icmp ult i64 %y, 11
+  ret i1 %z
+}
+
+define i1 @test_negative_combined_sub_signed_overflow(i8 %x) {
+; CHECK-LABEL: @test_negative_combined_sub_signed_overflow(
+; CHECK-NEXT:    [[Y:%.*]] = sub nsw i8 127, [[X:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = icmp slt i8 [[Y]], -1
+; CHECK-NEXT:    ret i1 [[Z]]
+;
+  %y = sub nsw i8 127, %x
+  %z = icmp slt i8 %y, -1
+  ret i1 %z
+}