From: Tim Northover Date: Wed, 19 Jul 2017 22:11:08 +0000 (+0000) Subject: GlobalISel: partially revert r308540. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f54b9c71c77bde497fce22277cad0f82c626962c;p=llvm GlobalISel: partially revert r308540. An unfinished and untested implementation of ISel for G_UNMERGE_VALUES crept in by mistake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308542 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index 148e973bb1c..58a261f749f 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -780,30 +780,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { return constrainSelectedInstRegOperands(I, TII, TRI, RBI); } - case TargetOpcode::G_UNMERGE_VALUES: { - // - LLT SrcTy = MRI.getType(I.getOperand(1).getReg()); - // Larger extracts are vectors, same-size extracts should be something else - // by now (either split up or simplified to a COPY). - if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32) - return false; - - I.setDesc(TII.get(AArch64::UBFMXri)); - MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() + - Ty.getSizeInBits() - 1); - - unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); - BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(), - TII.get(AArch64::COPY)) - .addDef(I.getOperand(0).getReg()) - .addUse(DstReg, 0, AArch64::sub_32); - RBI.constrainGenericRegister(I.getOperand(0).getReg(), - AArch64::GPR32RegClass, MRI); - I.getOperand(0).setReg(DstReg); - - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); - } - case TargetOpcode::G_INSERT: { LLT SrcTy = MRI.getType(I.getOperand(2).getReg()); // Larger inserts are vectors, same-size ones should be something else by