From: Craig Topper <craig.topper@intel.com>
Date: Tue, 27 Nov 2018 18:05:14 +0000 (+0000)
Subject: [X86] Add -march=cascadelake support in clang.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f5025150c044604d799e8d8f6b1e3340aaa37d20;p=clang

[X86] Add -march=cascadelake support in clang.

This is skylake-avx512 with the addition of avx512vnni ISA.

Patch by Jianping Chen

Differential Revision: https://reviews.llvm.org/D54792

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@347682 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/clang/Basic/X86Target.def b/include/clang/Basic/X86Target.def
index 4ffe6427a8..8c203c4db2 100644
--- a/include/clang/Basic/X86Target.def
+++ b/include/clang/Basic/X86Target.def
@@ -154,6 +154,10 @@ PROC_WITH_FEAT(SkylakeClient, "skylake", PROC_64_BIT, FEATURE_AVX2)
 PROC_WITH_FEAT(SkylakeServer, "skylake-avx512", PROC_64_BIT, FEATURE_AVX512F)
 PROC_ALIAS(SkylakeServer, "skx")
 
+/// \name Cascadelake Server
+/// Cascadelake Server microarchitecture based processors.
+PROC_WITH_FEAT(Cascadelake, "cascadelake", PROC_64_BIT, FEATURE_AVX512VNNI)
+
 /// \name Cannonlake Client
 /// Cannonlake client microarchitecture based processors.
 PROC_WITH_FEAT(Cannonlake, "cannonlake", PROC_64_BIT, FEATURE_AVX512VBMI)
diff --git a/lib/Basic/Targets/X86.cpp b/lib/Basic/Targets/X86.cpp
index c7f84e5266..53b4c153e9 100644
--- a/lib/Basic/Targets/X86.cpp
+++ b/lib/Basic/Targets/X86.cpp
@@ -142,7 +142,6 @@ bool X86TargetInfo::initFeatureMap(
     setFeatureEnabledImpl(Features, "gfni", true);
     setFeatureEnabledImpl(Features, "vpclmulqdq", true);
     setFeatureEnabledImpl(Features, "avx512bitalg", true);
-    setFeatureEnabledImpl(Features, "avx512vnni", true);
     setFeatureEnabledImpl(Features, "avx512vbmi2", true);
     setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
     setFeatureEnabledImpl(Features, "rdpid", true);
@@ -152,6 +151,12 @@ bool X86TargetInfo::initFeatureMap(
     setFeatureEnabledImpl(Features, "avx512vbmi", true);
     setFeatureEnabledImpl(Features, "sha", true);
     LLVM_FALLTHROUGH;
+  case CK_Cascadelake:
+    //Cannonlake has no VNNI feature inside while Icelake has
+    if (Kind != CK_Cannonlake)
+      // CLK inherits all SKX features plus AVX512_VNNI
+      setFeatureEnabledImpl(Features, "avx512vnni", true);
+    LLVM_FALLTHROUGH;
   case CK_SkylakeServer:
     setFeatureEnabledImpl(Features, "avx512f", true);
     setFeatureEnabledImpl(Features, "avx512cd", true);
@@ -166,7 +171,9 @@ bool X86TargetInfo::initFeatureMap(
     setFeatureEnabledImpl(Features, "xsavec", true);
     setFeatureEnabledImpl(Features, "xsaves", true);
     setFeatureEnabledImpl(Features, "mpx", true);
-    if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX
+    if (Kind != CK_SkylakeServer
+        && Kind != CK_Cascadelake)
+      // SKX/CLX inherits all SKL features, except SGX
       setFeatureEnabledImpl(Features, "sgx", true);
     setFeatureEnabledImpl(Features, "clflushopt", true);
     setFeatureEnabledImpl(Features, "aes", true);
@@ -949,6 +956,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   case CK_Broadwell:
   case CK_SkylakeClient:
   case CK_SkylakeServer:
+  case CK_Cascadelake:
   case CK_Cannonlake:
   case CK_IcelakeClient:
   case CK_IcelakeServer:
diff --git a/test/Driver/x86-march.c b/test/Driver/x86-march.c
index d0cd5b61d9..bc1194ff73 100644
--- a/test/Driver/x86-march.c
+++ b/test/Driver/x86-march.c
@@ -48,6 +48,10 @@
 // RUN:   | FileCheck %s -check-prefix=skx
 // skx: "-target-cpu" "skx"
 //
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=cascadelake 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=cascadelake
+// cascadelake: "-target-cpu" "cascadelake"
+//
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=knl 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=knl
 // knl: "-target-cpu" "knl"
diff --git a/test/Misc/target-invalid-cpu-note.c b/test/Misc/target-invalid-cpu-note.c
index 931f47a82c..170efb5497 100644
--- a/test/Misc/target-invalid-cpu-note.c
+++ b/test/Misc/target-invalid-cpu-note.c
@@ -16,7 +16,7 @@
 // X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
 // X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
 // X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// X86-SAME: skx, cannonlake, icelake-client, icelake-server, knl, knm, lakemont, k6, k6-2, k6-3,
+// X86-SAME: skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, lakemont, k6, k6-2, k6-3,
 // X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
 // X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
 // X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1,
@@ -27,7 +27,7 @@
 // X86_64: note: valid target CPU values are: nocona, core2, penryn, bonnell,
 // X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere,
 // X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell,
-// X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cannonlake,
+// X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake,
 // X86_64-SAME: icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
 // X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1,
 // X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, x86-64
diff --git a/test/Preprocessor/predefined-arch-macros.c b/test/Preprocessor/predefined-arch-macros.c
index c70ebf3708..65d3a3ec31 100644
--- a/test/Preprocessor/predefined-arch-macros.c
+++ b/test/Preprocessor/predefined-arch-macros.c
@@ -968,6 +968,103 @@
 // CHECK_SKX_M64: #define __x86_64 1
 // CHECK_SKX_M64: #define __x86_64__ 1
 
+// RUN: %clang -march=cascadelake -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_CLX_M32
+// CHECK_CLX_M32: #define __AES__ 1
+// CHECK_CLX_M32: #define __AVX2__ 1
+// CHECK_CLX_M32: #define __AVX512BW__ 1
+// CHECK_CLX_M32: #define __AVX512CD__ 1
+// CHECK_CLX_M32: #define __AVX512DQ__ 1
+// CHECK_CLX_M32: #define __AVX512F__ 1
+// CHECK_CLX_M32: #define __AVX512VL__ 1
+// CHECK_CLX_M32: #define __AVX512VNNI__ 1
+// CHECK_CLX_M32: #define __AVX__ 1
+// CHECK_CLX_M32: #define __BMI2__ 1
+// CHECK_CLX_M32: #define __BMI__ 1
+// CHECK_CLX_M32: #define __CLFLUSHOPT__ 1
+// CHECK_CLX_M32: #define __CLWB__ 1
+// CHECK_CLX_M32: #define __F16C__ 1
+// CHECK_CLX_M32: #define __FMA__ 1
+// CHECK_CLX_M32: #define __INVPCID__ 1
+// CHECK_CLX_M32: #define __LZCNT__ 1
+// CHECK_CLX_M32: #define __MMX__ 1
+// CHECK_CLX_M32: #define __MOVBE__ 1
+// CHECK_CLX_M32: #define __MPX__ 1
+// CHECK_CLX_M32: #define __PCLMUL__ 1
+// CHECK_CLX_M32: #define __PKU__ 1
+// CHECK_CLX_M32: #define __POPCNT__ 1
+// CHECK_CLX_M32: #define __PRFCHW__ 1
+// CHECK_CLX_M32: #define __RDRND__ 1
+// CHECK_CLX_M32: #define __RDSEED__ 1
+// CHECK_CLX_M32-NOT: #define __SGX__ 1
+// CHECK_CLX_M32: #define __SSE2__ 1
+// CHECK_CLX_M32: #define __SSE3__ 1
+// CHECK_CLX_M32: #define __SSE4_1__ 1
+// CHECK_CLX_M32: #define __SSE4_2__ 1
+// CHECK_CLX_M32: #define __SSE__ 1
+// CHECK_CLX_M32: #define __SSSE3__ 1
+// CHECK_CLX_M32: #define __XSAVEC__ 1
+// CHECK_CLX_M32: #define __XSAVEOPT__ 1
+// CHECK_CLX_M32: #define __XSAVES__ 1
+// CHECK_CLX_M32: #define __XSAVE__ 1
+// CHECK_CLX_M32: #define __corei7 1
+// CHECK_CLX_M32: #define __corei7__ 1
+// CHECK_CLX_M32: #define __i386 1
+// CHECK_CLX_M32: #define __i386__ 1
+// CHECK_CLX_M32: #define __tune_corei7__ 1
+// CHECK_CLX_M32: #define i386 1
+
+// RUN: %clang -march=cascadelake -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_CLX_M64
+// CHECK_CLX_M64: #define __AES__ 1
+// CHECK_CLX_M64: #define __AVX2__ 1
+// CHECK_CLX_M64: #define __AVX512BW__ 1
+// CHECK_CLX_M64: #define __AVX512CD__ 1
+// CHECK_CLX_M64: #define __AVX512DQ__ 1
+// CHECK_CLX_M64: #define __AVX512F__ 1
+// CHECK_CLX_M64: #define __AVX512VL__ 1
+// CHECK_CLX_M64: #define __AVX512VNNI__ 1
+// CHECK_CLX_M64: #define __AVX__ 1
+// CHECK_CLX_M64: #define __BMI2__ 1
+// CHECK_CLX_M64: #define __BMI__ 1
+// CHECK_CLX_M64: #define __CLFLUSHOPT__ 1
+// CHECK_CLX_M64: #define __CLWB__ 1
+// CHECK_CLX_M64: #define __F16C__ 1
+// CHECK_CLX_M64: #define __FMA__ 1
+// CHECK_CLX_M64: #define __INVPCID__ 1
+// CHECK_CLX_M64: #define __LZCNT__ 1
+// CHECK_CLX_M64: #define __MMX__ 1
+// CHECK_CLX_M64: #define __MOVBE__ 1
+// CHECK_CLX_M64: #define __MPX__ 1
+// CHECK_CLX_M64: #define __PCLMUL__ 1
+// CHECK_CLX_M64: #define __PKU__ 1
+// CHECK_CLX_M64: #define __POPCNT__ 1
+// CHECK_CLX_M64: #define __PRFCHW__ 1
+// CHECK_CLX_M64: #define __RDRND__ 1
+// CHECK_CLX_M64: #define __RDSEED__ 1
+// CHECK_CLX_M64-NOT: #define __SGX__ 1
+// CHECK_CLX_M64: #define __SSE2_MATH__ 1
+// CHECK_CLX_M64: #define __SSE2__ 1
+// CHECK_CLX_M64: #define __SSE3__ 1
+// CHECK_CLX_M64: #define __SSE4_1__ 1
+// CHECK_CLX_M64: #define __SSE4_2__ 1
+// CHECK_CLX_M64: #define __SSE_MATH__ 1
+// CHECK_CLX_M64: #define __SSE__ 1
+// CHECK_CLX_M64: #define __SSSE3__ 1
+// CHECK_CLX_M64: #define __XSAVEC__ 1
+// CHECK_CLX_M64: #define __XSAVEOPT__ 1
+// CHECK_CLX_M64: #define __XSAVES__ 1
+// CHECK_CLX_M64: #define __XSAVE__ 1
+// CHECK_CLX_M64: #define __amd64 1
+// CHECK_CLX_M64: #define __amd64__ 1
+// CHECK_CLX_M64: #define __corei7 1
+// CHECK_CLX_M64: #define __corei7__ 1
+// CHECK_CLX_M64: #define __tune_corei7__ 1
+// CHECK_CLX_M64: #define __x86_64 1
+// CHECK_CLX_M64: #define __x86_64__ 1
+
 // RUN: %clang -march=cannonlake -m32 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_CNL_M32