From: Cullen Rhodes <cullen.rhodes@arm.com>
Date: Mon, 29 Apr 2019 15:27:27 +0000 (+0000)
Subject: [AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f3de5a58e629d952b68b1911af9e5ed8fe290496;p=llvm

[AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions

This patch adds aliases for element sizes .B/.H/.S to the
AND/ORR/EOR/BIC bitwise logical instructions. The assembler now accepts
these instructions with all element sizes up to 64-bit (.D). The
preferred disassembly is .D.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359457 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 655caa3deb5..1d099cbba98 100644
--- a/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -25,10 +25,10 @@ let Predicates = [HasSVE] in {
   defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">;
   defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">;
 
-  def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
-  def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
-  def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
-  def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
+  defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
+  defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
+  defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
+  defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
 
   defm ADD_ZPmZ   : sve_int_bin_pred_arit_0<0b000, "add">;
   defm SUB_ZPmZ   : sve_int_bin_pred_arit_0<0b001, "sub">;
diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
index 3a3efaa96ce..81c4e4c76e6 100644
--- a/lib/Target/AArch64/SVEInstrFormats.td
+++ b/lib/Target/AArch64/SVEInstrFormats.td
@@ -1982,6 +1982,16 @@ class sve_int_bin_cons_log<bits<2> opc, string asm>
   let Inst{4-0}   = Zd;
 }
 
+multiclass sve_int_bin_cons_log<bits<2> opc, string asm> {
+  def NAME : sve_int_bin_cons_log<opc, asm>;
+
+  def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+                  (!cast<Instruction>(NAME) ZPR8:$Zd,  ZPR8:$Zn,  ZPR8:$Zm),  1>;
+  def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+                  (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>;
+  def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
+                  (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>;
+}
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Wide Immediate - Predicated Group
diff --git a/test/MC/AArch64/SVE/and.s b/test/MC/AArch64/SVE/and.s
index 0d0edc73e8f..0dc99ab2be9 100644
--- a/test/MC/AArch64/SVE/and.s
+++ b/test/MC/AArch64/SVE/and.s
@@ -110,6 +110,28 @@ and     p15.b, p15/z, p15.b, p15.b
 // CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
 
 
+// --------------------------------------------------------------------------//
+// Test aliases.
+
+and     z0.s, z0.s, z0.s
+// CHECK-INST: and     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+and     z0.h, z0.h, z0.h
+// CHECK-INST: and     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+and     z0.b, z0.b, z0.b
+// CHECK-INST: and     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
diff --git a/test/MC/AArch64/SVE/bic.s b/test/MC/AArch64/SVE/bic.s
index c9e6d9b8266..064e295a9c6 100644
--- a/test/MC/AArch64/SVE/bic.s
+++ b/test/MC/AArch64/SVE/bic.s
@@ -104,6 +104,28 @@ bic     p0.b, p0/z, p0.b, p0.b
 // CHECK-UNKNOWN: 10 40 00 25 <unknown>
 
 
+// --------------------------------------------------------------------------//
+// Test aliases.
+
+bic     z0.s, z0.s, z0.s
+// CHECK-INST: bic     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+bic     z0.h, z0.h, z0.h
+// CHECK-INST: bic     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+bic     z0.b, z0.b, z0.b
+// CHECK-INST: bic     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
diff --git a/test/MC/AArch64/SVE/eor.s b/test/MC/AArch64/SVE/eor.s
index f7b4247ad80..e2c41ce5fed 100644
--- a/test/MC/AArch64/SVE/eor.s
+++ b/test/MC/AArch64/SVE/eor.s
@@ -110,6 +110,28 @@ eor     p15.b, p15/z, p15.b, p15.b
 // CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
 
 
+// --------------------------------------------------------------------------//
+// Test aliases.
+
+eor     z0.s, z0.s, z0.s
+// CHECK-INST: eor     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+eor     z0.h, z0.h, z0.h
+// CHECK-INST: eor     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+eor     z0.b, z0.b, z0.b
+// CHECK-INST: eor     z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
diff --git a/test/MC/AArch64/SVE/orr.s b/test/MC/AArch64/SVE/orr.s
index 7d00cd8c6cf..084587787ba 100644
--- a/test/MC/AArch64/SVE/orr.s
+++ b/test/MC/AArch64/SVE/orr.s
@@ -112,6 +112,46 @@ orr     p15.b, p15/z, p15.b, p15.b
 // CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
 
 
+// --------------------------------------------------------------------------//
+// Test aliases.
+
+orr     z0.s, z0.s, z0.s
+// CHECK-INST: mov     z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr     z0.h, z0.h, z0.h
+// CHECK-INST: mov     z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr     z0.b, z0.b, z0.b
+// CHECK-INST: mov     z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr     z23.s, z13.s, z8.s  // should not use mov-alias
+// CHECK-INST: orr     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+orr     z23.h, z13.h, z8.h  // should not use mov-alias
+// CHECK-INST: orr     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+orr     z23.b, z13.b, z8.b  // should not use mov-alias
+// CHECK-INST: orr     z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.