From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 17 Dec 2018 21:36:17 +0000 (+0000)
Subject: [X86][SSE] Split SimplifyDemandedBitsForTargetNode X86ISD::VSRLI/VSRAI handling.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f3b65bc4f2f999d7e50a73dfafc0539a35fd1cb6;p=llvm

[X86][SSE] Split SimplifyDemandedBitsForTargetNode X86ISD::VSRLI/VSRAI handling.

First step towards adding more capable combines to fix comments in D55768.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349400 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 757fe86935c..92542198677 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -32410,8 +32410,22 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
     }
     break;
   }
-  case X86ISD::VSRAI:
   case X86ISD::VSRLI: {
+    if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      if (ShiftImm->getAPIntValue().uge(BitWidth))
+        break;
+
+      KnownBits KnownOp;
+      unsigned ShAmt = ShiftImm->getZExtValue();
+      APInt DemandedMask = OriginalDemandedBits << ShAmt;
+
+      if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
+                               OriginalDemandedElts, KnownOp, TLO, Depth + 1))
+        return true;
+    }
+    break;
+  }
+  case X86ISD::VSRAI: {
     if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
       if (ShiftImm->getAPIntValue().uge(BitWidth))
         break;
@@ -32422,8 +32436,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
 
       // If any of the demanded bits are produced by the sign extension, we also
       // demand the input sign bit.
-      if (Opc == X86ISD::VSRAI &&
-          OriginalDemandedBits.countLeadingZeros() < ShAmt)
+      if (OriginalDemandedBits.countLeadingZeros() < ShAmt)
         DemandedMask.setSignBit();
 
       if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,