From: Simon Atanasyan <simon@atanasyan.com>
Date: Thu, 12 Jul 2018 08:50:11 +0000 (+0000)
Subject: [mips] Mark standard encoded instructions as not being in MIPS16e
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f35639b8448bce1d8c0fd2dadc805c608b61dcb5;p=llvm

[mips] Mark standard encoded instructions as not being in MIPS16e

Mark standard encoded instructions and pseudo "standard encoded"
as not being in MIPS16e by default.

Patch by Simon Dardis.

Differential revision: https://reviews.llvm.org/D48379

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336893 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index 04bb7101014..ebbdcdf0df8 100644
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -120,7 +120,7 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
              InstrItinClass itin, Format f, string opstr = ""> :
   MipsInst<outs, ins, asmstr, pattern, itin, f> {
-  let EncodingPredicates = [HasStdEnc];
+  let EncodingPredicates = [NotInMips16Mode];
   string BaseOpcode = opstr;
   string Arch;
 }
@@ -137,7 +137,7 @@ class MipsPseudo<dag outs, dag ins, list<dag> pattern,
 class PseudoSE<dag outs, dag ins, list<dag> pattern,
                InstrItinClass itin = IIPseudo> :
   MipsPseudo<outs, ins, pattern, itin> {
-  let EncodingPredicates = [HasStdEnc];
+  let EncodingPredicates = [NotInMips16Mode];
 }
 
 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td
index 34209d5871e..f43f5d74ead 100644
--- a/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -3752,7 +3752,7 @@ def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
 
 // Pseudoes used to implement transparent fp16 support.
 
-let Predicates = [HasMSA] in {
+let ASEPredicate = [HasMSA] in {
  def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
                           [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> {
    let usesCustomInserter = 1;