From: Alex Bradbury Date: Mon, 11 Mar 2019 20:43:29 +0000 (+0000) Subject: [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator() X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f3044fe69631433b02807a5248820dccb662ffa6;p=llvm [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355864 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp index 60041da0694..9b4193e53e1 100644 --- a/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/lib/Target/RISCV/RISCVISelLowering.cpp @@ -813,8 +813,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI, F->insert(I, IfFalseMBB); F->insert(I, TailMBB); // Move all remaining instructions to TailMBB. - TailMBB->splice(TailMBB->begin(), HeadMBB, - std::next(MachineBasicBlock::iterator(MI)), HeadMBB->end()); + TailMBB->splice(TailMBB->begin(), HeadMBB, std::next(MI.getIterator()), + HeadMBB->end()); // Update machine-CFG edges by transferring all successors of the current // block to the new block which will contain the Phi node for the select. TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB); diff --git a/lib/Target/RISCV/RISCVInstrInfo.cpp b/lib/Target/RISCV/RISCVInstrInfo.cpp index ddb976b47fb..dc63c51b4bc 100644 --- a/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -382,8 +382,8 @@ unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, .addMBB(&DestBB, RISCVII::MO_LO); RS->enterBasicBlockEnd(MBB); - unsigned Scav = RS->scavengeRegisterBackwards( - RISCV::GPRRegClass, MachineBasicBlock::iterator(LuiMI), false, 0); + unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass, + LuiMI.getIterator(), false, 0); MRI.replaceRegWith(ScratchReg, Scav); MRI.clearVirtRegs(); RS->setRegUsed(Scav);