From: Sanjay Patel <spatel@rotateright.com>
Date: Mon, 8 Apr 2019 13:28:29 +0000 (+0000)
Subject: [InstCombine] remove overzealous assert for shuffles (PR41419)
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f2bfd1e2c62f2f92eca7afa8f50ae1b6007eda1c;p=llvm

[InstCombine] remove overzealous assert for shuffles (PR41419)

As the TODO indicates, instsimplify could be improved.

Should fix:
https://bugs.llvm.org/show_bug.cgi?id=41419

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357910 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
index 665064c4c8d..28d5f187c3d 100644
--- a/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+++ b/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
@@ -1353,8 +1353,8 @@ static Instruction *foldSelectShuffle(ShuffleVectorInst &Shuf,
   // Canonicalize to choose from operand 0 first.
   unsigned NumElts = Shuf.getType()->getVectorNumElements();
   if (Shuf.getMaskValue(0) >= (int)NumElts) {
-    assert(!isa<UndefValue>(Shuf.getOperand(1)) &&
-           "Not expecting undef shuffle operand with select mask");
+    // TODO: Can we assert that both operands of a shuffle-select are not undef
+    // (otherwise, it would have been folded by instsimplify?
     Shuf.commute();
     return &Shuf;
   }
diff --git a/test/Transforms/InstCombine/shuffle_select.ll b/test/Transforms/InstCombine/shuffle_select.ll
index 991f390682a..6cda586f913 100644
--- a/test/Transforms/InstCombine/shuffle_select.ll
+++ b/test/Transforms/InstCombine/shuffle_select.ll
@@ -1454,3 +1454,13 @@ define <4 x i8> @or_add_2_vars(<4 x i8> %v, <4 x i8> %v1) {
   ret <4 x i8> %t3
 }
 
+; The undef operand is used to simplify the shuffle mask, but don't assert that too soon.
+
+define <4 x i32> @PR41419(<4 x i32> %v) {
+; CHECK-LABEL: @PR41419(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %s = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+  ret <4 x i32> %s
+}
+