From: Konstantin Zhuravlyov <kzhuravl_dev@outlook.com>
Date: Fri, 21 Jul 2017 21:05:45 +0000 (+0000)
Subject: AMDGPU: Introduce maybeAtomic instruction flag
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f15f5487f2d72b1bd0a5803cbf107e9bb6130ffa;p=llvm

AMDGPU: Introduce maybeAtomic instruction flag

Testing is in the follow up change


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308779 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/BUFInstructions.td b/lib/Target/AMDGPU/BUFInstructions.td
index 0354a609f4e..89caa65cdaf 100644
--- a/lib/Target/AMDGPU/BUFInstructions.td
+++ b/lib/Target/AMDGPU/BUFInstructions.td
@@ -437,6 +437,7 @@ class MUBUF_Load_Pseudo <string opName,
   let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
   let mayLoad = 1;
   let mayStore = 0;
+  let maybeAtomic = 1;
 }
 
 // FIXME: tfe can't be an operand because it requires a separate
@@ -483,6 +484,7 @@ class MUBUF_Store_Pseudo <string opName,
   let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
   let mayLoad = 0;
   let mayStore = 1;
+  let maybeAtomic = 1;
 }
 
 multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
@@ -566,6 +568,7 @@ class MUBUF_Atomic_Pseudo<string opName,
   let DisableWQM = 1;
   let has_glc = 0;
   let has_tfe = 0;
+  let maybeAtomic = 1;
 }
 
 class MUBUF_AtomicNoRet_Pseudo<string opName, int addrKind,
diff --git a/lib/Target/AMDGPU/FLATInstructions.td b/lib/Target/AMDGPU/FLATInstructions.td
index fcfd629d55e..b038cc4fa2c 100644
--- a/lib/Target/AMDGPU/FLATInstructions.td
+++ b/lib/Target/AMDGPU/FLATInstructions.td
@@ -137,6 +137,7 @@ class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
   let has_saddr = HasSaddr;
   let enabled_saddr = EnableSaddr;
   let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
+  let maybeAtomic = 1;
 }
 
 class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
@@ -157,6 +158,7 @@ class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
   let has_saddr = HasSaddr;
   let enabled_saddr = EnableSaddr;
   let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
+  let maybeAtomic = 1;
 }
 
 multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass> {
@@ -187,6 +189,7 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
   let enabled_saddr = EnableSaddr;
   let has_vaddr = !if(EnableSaddr, 0, 1);
   let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
+  let maybeAtomic = 1;
 }
 
 class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0> : FLAT_Pseudo<
@@ -202,8 +205,8 @@ class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit En
   let has_saddr = 1;
   let enabled_saddr = EnableSaddr;
   let has_vaddr = !if(EnableSaddr, 0, 1);
-
   let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
+  let maybeAtomic = 1;
 }
 
 multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass> {
@@ -228,6 +231,7 @@ class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
     let has_glc  = 0;
     let glcValue = 0;
     let has_vdst = 0;
+    let maybeAtomic = 1;
 }
 
 class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
diff --git a/lib/Target/AMDGPU/SIDefines.h b/lib/Target/AMDGPU/SIDefines.h
index e86d4b4d1e0..1d151243f7d 100644
--- a/lib/Target/AMDGPU/SIDefines.h
+++ b/lib/Target/AMDGPU/SIDefines.h
@@ -68,7 +68,8 @@ enum : uint64_t {
   FIXED_SIZE = UINT64_C(1) << 40,
   VOPAsmPrefer32Bit = UINT64_C(1) << 41,
   HasFPClamp = UINT64_C(1) << 42,
-  VOP3_OPSEL = UINT64_C(1) << 43
+  VOP3_OPSEL = UINT64_C(1) << 43,
+  maybeAtomic = UINT64_C(1) << 44
 };
 
 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
diff --git a/lib/Target/AMDGPU/SIInstrFormats.td b/lib/Target/AMDGPU/SIInstrFormats.td
index aa491ea1965..f2e1437ae6b 100644
--- a/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/lib/Target/AMDGPU/SIInstrFormats.td
@@ -45,7 +45,7 @@ class InstSI <dag outs, dag ins, string asm = "",
   field bit FLAT = 0;
   field bit DS = 0;
 
-   // Pseudo instruction formats.
+  // Pseudo instruction formats.
   field bit VGPRSpill = 0;
   field bit SGPRSpill = 0;
 
@@ -87,6 +87,9 @@ class InstSI <dag outs, dag ins, string asm = "",
   // modifier (gfx9 only).
   field bit VOP3_OPSEL = 0;
 
+  // Is it possible for this instruction to be atomic?
+  field bit maybeAtomic = 0;
+
   // These need to be kept in sync with the enum in SIInstrFlags.
   let TSFlags{0} = SALU;
   let TSFlags{1} = VALU;
@@ -133,6 +136,8 @@ class InstSI <dag outs, dag ins, string asm = "",
   let TSFlags{42} = FPClamp;
   let TSFlags{43} = VOP3_OPSEL;
 
+  let TSFlags{44} = maybeAtomic;
+
   let SchedRW = [Write32Bit];
 
   field bits<1> DisableSIDecoder = 0;
diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index 5826874d3c4..f6b723d3474 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -99,6 +99,7 @@ def ATOMIC_FENCE : SPseudoInstSI<
   [(atomic_fence (i32 imm:$ordering), (i32 imm:$scope))],
   "ATOMIC_FENCE $ordering, $scope"> {
   let hasSideEffects = 1;
+  let maybeAtomic = 1;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {