From: David Green <david.green@arm.com>
Date: Sun, 26 May 2019 10:42:24 +0000 (+0000)
Subject: [ARM] Select fp16 fsqrt
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f0ac52c9d3cce21ce0e584871827390d358c4c5b;p=llvm

[ARM] Select fp16 fsqrt

This adds a pattern for the sqrt intrinsic, the same as float and double.

Differential Revision: https://reviews.llvm.org/D62322


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361714 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 4478fce6ef9..17f954ef7dd 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -1023,9 +1023,9 @@ def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
              Sched<[WriteFPSQRT32]>;
 
 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sm),
                   IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
-                  []>;
+                  [(set HPR:$Sd, (fsqrt (f16 HPR:$Sm)))]>;
 
 let hasSideEffects = 0 in {
 let isMoveReg = 1 in {
diff --git a/test/CodeGen/ARM/fp16-fullfp16.ll b/test/CodeGen/ARM/fp16-fullfp16.ll
index d5ded1febe4..e4a8fa75504 100644
--- a/test/CodeGen/ARM/fp16-fullfp16.ll
+++ b/test/CodeGen/ARM/fp16-fullfp16.ll
@@ -217,13 +217,17 @@ define void @test_bitcast_i16tohalf(i16 %a, half* %p) {
   ret void
 }
 
-; FIXME
-;define void @test_sqrt(half* %p) {
-;  %a = load half, half* %p, align 2
-;  %r = call half @llvm.sqrt.f16(half %a)
-;  store half %r, half* %p
-;  ret void
-;}
+define void @test_sqrt(half* %p) {
+; CHECK-LABEL: test_sqrt:
+; CHECK:         vldr.16 s0, [r0]
+; CHECK-NEXT:    vsqrt.f16 s0, s0
+; CHECK-NEXT:    vstr.16 s0, [r0]
+; CHECK-NEXT:    bx lr
+  %a = load half, half* %p, align 2
+  %r = call half @llvm.sqrt.f16(half %a)
+  store half %r, half* %p
+  ret void
+}
 
 ; FIXME
 ;define void @test_fpowi(half* %p, i32 %b) {