From: Tim Northover <tnorthover@apple.com>
Date: Mon, 30 Jan 2017 20:52:42 +0000 (+0000)
Subject: GlobalISel: account for differing exception selector sizes.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f06702d6ea27692ec36a960dd2928acd9fe984ce;p=llvm

GlobalISel: account for differing exception selector sizes.

For some reason the exception selector register must be a pointer (that's
assumed by SDag); on the other hand, it gets moved into an IR-level type which
might be entirely different (i32 on AArch64). IRTranslator needs to be aware of
this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293546 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/GlobalISel/IRTranslator.cpp b/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 3a2469dca49..21657827a93 100644
--- a/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -801,8 +801,17 @@ bool IRTranslator::translateLandingPad(const User &U,
 
   if (unsigned Reg = TLI.getExceptionSelectorRegister(PersonalityFn)) {
     MBB.addLiveIn(Reg);
+
+    // N.b. the exception selector register always has pointer type and may not
+    // match the actual IR-level type in the landingpad so an extra cast is
+    // needed.
+    unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
+    MIRBuilder.buildCopy(PtrVReg, Reg);
+
     unsigned VReg = MRI->createGenericVirtualRegister(Tys[1]);
-    MIRBuilder.buildCopy(VReg, Reg);
+    MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
+        .addDef(VReg)
+        .addUse(PtrVReg);
     Regs.push_back(VReg);
     Offsets.push_back(Tys[0].getSizeInBits());
   }
diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index 2f252376309..f5eacda8b09 100644
--- a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -19,7 +19,8 @@ declare i32 @llvm.eh.typeid.for(i8*)
 ; CHECK:   [[BAD]] (landing-pad):
 ; CHECK:     EH_LABEL
 ; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK:     [[SEL:%[0-9]+]](s32) = COPY %x1
+; CHECK:     [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
+; CHECK:     [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
 ; CHECK:     [[PTR_SEL:%[0-9]+]](s128) = G_SEQUENCE [[PTR]](p0), 0, [[SEL]](s32), 64
 ; CHECK:     [[PTR_RET:%[0-9]+]](s64), [[SEL_RET:%[0-9]+]](s32) = G_EXTRACT [[PTR_SEL]](s128), 0, 64
 ; CHECK:     %x0 = COPY [[PTR_RET]]
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index 7e32a25f1dd..001aea6409b 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -15,7 +15,8 @@ declare void @_Unwind_Resume(i8*)
 ; CHECK:   [[LP]] (landing-pad):
 ; CHECK:     EH_LABEL
 ; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK:     [[SEL:%[0-9]+]](s32) = COPY %x1
+; CHECK:     [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
+; CHECK:     [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
 ; CHECK-NOT: G_SEQUENCE
 ; CHECK-NOT: G_EXTRACT
 ; CHECK:     G_STORE [[PTR]](p0), {{%[0-9]+}}(p0)