From: Guy Blank <guy.blank@intel.com>
Date: Mon, 19 Jun 2017 08:58:13 +0000 (+0000)
Subject: [X86] Simplify vector-shuffle-v48 test. NFC.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=f00ca4f77d23c015d84ab09c02f7d136ffb187ea;p=llvm

[X86] Simplify vector-shuffle-v48 test. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305670 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/vector-shuffle-v48.ll b/test/CodeGen/X86/vector-shuffle-v48.ll
index 9bd75148ecd..885b5c86ee8 100644
--- a/test/CodeGen/X86/vector-shuffle-v48.ll
+++ b/test/CodeGen/X86/vector-shuffle-v48.ll
@@ -1,49 +1,46 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-pc-linux  -mattr=+avx2 < %s | FileCheck %s
-define <16 x i8> @foo(<48 x i8>* %x0, <16 x i32> %x1, <16 x i32> %x2) {
+define <32 x i8> @foo(<48 x i8>* %x0, <16 x i32> %x1, <16 x i32> %x2) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    vmovdqu (%rdi), %ymm4
-; CHECK-NEXT:    vmovdqu 32(%rdi), %xmm5
-; CHECK-NEXT:    vpextrb $13, %xmm5, %eax
-; CHECK-NEXT:    vpextrb $10, %xmm5, %ecx
-; CHECK-NEXT:    vpextrb $7, %xmm5, %edx
-; CHECK-NEXT:    vpextrb $4, %xmm5, %esi
-; CHECK-NEXT:    vpextrb $1, %xmm5, %edi
-; CHECK-NEXT:    vextracti128 $1, %ymm4, %xmm5
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm6 = xmm5[2,2,5,5,5,5,3,3,4,4,5,5,6,6,7,7]
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm7 = xmm4[12,12,13,13,15,15,15,15,12,12,13,13,14,14,15,15]
-; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm6 = xmm7[0],xmm6[0]
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm4 = xmm4[0,0,1,1,3,3,3,3,6,6,9,9,9,9,7,7]
-; CHECK-NEXT:    vinserti128 $1, %xmm6, %ymm4, %ymm4
-; CHECK-NEXT:    vpand {{.*}}(%rip), %ymm4, %ymm4
-; CHECK-NEXT:    vpshufb {{.*#+}} xmm5 = xmm5[8,11,14],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT:    vpinsrb $3, %edi, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $4, %esi, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $5, %edx, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $6, %ecx, %xmm5, %xmm5
-; CHECK-NEXT:    vpinsrb $7, %eax, %xmm5, %xmm5
-; CHECK-NEXT:    vpmovzxbd {{.*#+}} ymm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero,xmm5[2],zero,zero,zero,xmm5[3],zero,zero,zero,xmm5[4],zero,zero,zero,xmm5[5],zero,zero,zero,xmm5[6],zero,zero,zero,xmm5[7],zero,zero,zero
-; CHECK-NEXT:    vpmulld %ymm0, %ymm4, %ymm0
-; CHECK-NEXT:    vpmulld %ymm1, %ymm5, %ymm1
-; CHECK-NEXT:    vpsrlvd %ymm2, %ymm0, %ymm0
-; CHECK-NEXT:    vpsrlvd %ymm3, %ymm1, %ymm1
-; CHECK-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
-; CHECK-NEXT:    vpshufb %ymm2, %ymm0, %ymm0
-; CHECK-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
-; CHECK-NEXT:    vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
-; CHECK-NEXT:    vpshufb %xmm3, %xmm0, %xmm0
-; CHECK-NEXT:    vpshufb %ymm2, %ymm1, %ymm1
-; CHECK-NEXT:    vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
-; CHECK-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
-; CHECK-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    vmovdqu 32(%rdi), %xmm0
+; CHECK-NEXT:    vmovdqu (%rdi), %ymm1
+; CHECK-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; CHECK-NEXT:    vpextrb $0, %xmm2, %eax
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm1 = xmm1[0,1,3,4,6,7,9,10,12,13,15],zero,zero,zero,zero,zero
+; CHECK-NEXT:    vpinsrb $11, %eax, %xmm1, %xmm1
+; CHECK-NEXT:    vpextrb $2, %xmm2, %eax
+; CHECK-NEXT:    vpinsrb $12, %eax, %xmm1, %xmm1
+; CHECK-NEXT:    vpextrb $3, %xmm2, %eax
+; CHECK-NEXT:    vpinsrb $13, %eax, %xmm1, %xmm1
+; CHECK-NEXT:    vpextrb $5, %xmm2, %eax
+; CHECK-NEXT:    vpinsrb $14, %eax, %xmm1, %xmm1
+; CHECK-NEXT:    vpextrb $6, %xmm2, %eax
+; CHECK-NEXT:    vpinsrb $15, %eax, %xmm1, %xmm1
+; CHECK-NEXT:    vpextrb $1, %xmm0, %eax
+; CHECK-NEXT:    vpshufb {{.*#+}} xmm2 = xmm2[8,9,11,12,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT:    vpinsrb $6, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $2, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $7, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $4, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $8, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $5, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $9, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $7, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $10, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $8, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $11, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $10, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $12, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $11, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $13, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $13, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $14, %eax, %xmm2, %xmm2
+; CHECK-NEXT:    vpextrb $14, %xmm0, %eax
+; CHECK-NEXT:    vpinsrb $15, %eax, %xmm2, %xmm0
+; CHECK-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
   %1 = load <48 x i8>, <48 x i8>* %x0, align 1
-  %2 = shufflevector <48 x i8> %1, <48 x i8> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
-  %3 = zext <16 x i8> %2 to <16 x i32>
-  %4 = mul <16 x i32> %3, %x1
-  %5 = lshr <16 x i32> %4, %x2
-  %6 = trunc <16 x i32> %5 to <16 x i8>
-  ret <16 x i8> %6
+  %2 = shufflevector <48 x i8> %1, <48 x i8> undef, <32 x i32> <i32 0, i32 1, i32 3, i32 4, i32 6, i32 7, i32 9, i32 10, i32 12, i32 13, i32 15, i32 16, i32 18, i32 19, i32 21, i32 22, i32 24, i32 25, i32 27, i32 28, i32 30, i32 31, i32 33, i32 34, i32 36, i32 37, i32 39, i32 40, i32 42, i32 43, i32 45, i32 46>
+  ret <32 x i8> %2
 }