From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Thu, 19 Jul 2018 09:14:39 +0000 (+0000)
Subject: Fix spelling mistake in comments. NFCI.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ef2fcbd30cfc86cd73362921e624de9d0ded150a;p=llvm

Fix spelling mistake in comments. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337442 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index e9a9a996b03..8e4ac4ad888 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -724,7 +724,7 @@ let Predicates = [UseSSE1] in {
             (MOVLPSmr addr:$src1, VR128:$src2)>;
 
   // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
-  // end up with a movsd or bleand instead of shufp.
+  // end up with a movsd or blend instead of shufp.
   // No need for aligned load, we're only loading 64-bits.
   def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)),
             (MOVLPSrm VR128:$src1, addr:$src2)>;
@@ -780,7 +780,7 @@ let Predicates = [UseAVX] in {
 
 let Predicates = [UseSSE1] in {
   // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
-  // end up with a movsd or bleand instead of shufp.
+  // end up with a movsd or blend instead of shufp.
   // No need for aligned load, we're only loading 64-bits.
   def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)),
             (MOVHPSrm VR128:$src1, addr:$src2)>;