From: Petar Jovanovic Date: Wed, 7 Jun 2017 14:48:46 +0000 (+0000) Subject: [mips][dsp] Modify repl.ph to accept signed immediate values X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=eeb64a67b6dbad4ab2b1dc29481d5cbf41c7e448;p=llvm [mips][dsp] Modify repl.ph to accept signed immediate values Changed immediate type for repl.ph from uimm10 to simm10 as per the specs. Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of GNU as. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33594 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304918 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index ac9a81b1bb2..c238a65378e 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -19,6 +19,7 @@ def immZExt4 : ImmLeaf(Imm);}]>; def immZExt8 : ImmLeaf(Imm);}]>; def immZExt10 : ImmLeaf(Imm);}]>; def immSExt6 : ImmLeaf(Imm);}]>; +def immSExt10 : ImmLeaf(Imm);}]>; // Mips-specific dsp nodes def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, @@ -851,8 +852,8 @@ class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8, immZExt8, NoItinerary, DSPROpnd>; -class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, uimm10, - immZExt10, NoItinerary, DSPROpnd>; +class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10, + immSExt10, NoItinerary, DSPROpnd>; class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, NoItinerary, DSPROpnd, GPR32Opnd>; diff --git a/test/CodeGen/Mips/dsp-r1.ll b/test/CodeGen/Mips/dsp-r1.ll index edd6258270a..90eb14a75b4 100644 --- a/test/CodeGen/Mips/dsp-r1.ll +++ b/test/CodeGen/Mips/dsp-r1.ll @@ -1172,9 +1172,19 @@ entry: ret { i32 } %.fca.0.insert } +define { i32 } @test__builtin_mips_repl_ph2(i32 %i0) nounwind readnone { +entry: +; CHECK: repl.ph + + %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 -2) + %1 = bitcast <2 x i16> %0 to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone -define { i32 } @test__builtin_mips_repl_ph2(i32 %i0, i32 %a0) nounwind readnone { +define { i32 } @test__builtin_mips_repl_ph3(i32 %i0, i32 %a0) nounwind readnone { entry: ; CHECK: replv.ph diff --git a/test/MC/Disassembler/Mips/micromips-dsp/valid.txt b/test/MC/Disassembler/Mips/micromips-dsp/valid.txt index f3d6f3dc036..a373bcd9d6a 100644 --- a/test/MC/Disassembler/Mips/micromips-dsp/valid.txt +++ b/test/MC/Disassembler/Mips/micromips-dsp/valid.txt @@ -94,7 +94,7 @@ 0x00 0x01 0x70 0x7c # CHECK: mtlo $1, $ac1 0x00 0x22 0xf1 0x3c # CHECK: raddu.w.qb $1, $2 0x00 0x20 0x86 0x7c # CHECK: rddsp $1, 2 -0x02 0x00 0x08 0x3d # CHECK: repl.ph $1, 512 +0x00 0x02 0x08 0x3d # CHECK: repl.ph $1, 2 0x00 0x30 0x05 0xfc # CHECK: repl.qb $1, 128 0x00 0x22 0x03 0x3c # CHECK: replv.ph $1, $2 0x00 0x22 0x13 0x3c # CHECK: replv.qb $1, $2 diff --git a/test/MC/Mips/dsp/invalid.s b/test/MC/Mips/dsp/invalid.s index 1d50b829985..f58a44560c5 100644 --- a/test/MC/Mips/dsp/invalid.s +++ b/test/MC/Mips/dsp/invalid.s @@ -31,8 +31,8 @@ shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate repl.qb $2, -1 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate repl.qb $2, 256 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate - repl.ph $2, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate - repl.ph $2, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + repl.ph $2, -513 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate + repl.ph $2, 512 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate rddsp $2, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate rddsp $2, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate diff --git a/test/MC/Mips/micromips-dsp/invalid.s b/test/MC/Mips/micromips-dsp/invalid.s index 8e6fedbf0b9..05fc77440d3 100644 --- a/test/MC/Mips/micromips-dsp/invalid.s +++ b/test/MC/Mips/micromips-dsp/invalid.s @@ -1,6 +1,8 @@ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp 2>%t1 # RUN: FileCheck %s < %t1 + repl.ph $2, -513 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate + repl.ph $2, 512 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate shll.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shll.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shll_s.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate diff --git a/test/MC/Mips/micromips-dsp/valid.s b/test/MC/Mips/micromips-dsp/valid.s index d1f5d0f3ae8..ed279f3eb53 100644 --- a/test/MC/Mips/micromips-dsp/valid.s +++ b/test/MC/Mips/micromips-dsp/valid.s @@ -95,7 +95,7 @@ mtlo $1, $ac1 # CHECK: mtlo $1, $ac1 # encoding: [0x00,0x01,0x70,0x7c] raddu.w.qb $1, $2 # CHECK: raddu.w.qb $1, $2 # encoding: [0x00,0x22,0xf1,0x3c] rddsp $1, 2 # CHECK: rddsp $1, 2 # encoding: [0x00,0x20,0x86,0x7c] - repl.ph $1, 512 # CHECK: repl.ph $1, 512 # encoding: [0x02,0x00,0x08,0x3d] + repl.ph $1, 2 # CHECK: repl.ph $1, 2 # encoding: [0x00,0x02,0x08,0x3d] repl.qb $1, 128 # CHECK: repl.qb $1, 128 # encoding: [0x00,0x30,0x05,0xfc] replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x00,0x22,0x03,0x3c] replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x00,0x22,0x13,0x3c]