From: Sanjay Patel Date: Sat, 4 Mar 2017 20:35:19 +0000 (+0000) Subject: [x86] don't require a zext when forming ADC/SBB X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ecd4d5328147dad0d399f3f88868be33adee2d69;p=llvm [x86] don't require a zext when forming ADC/SBB The larger goal is to move the ADC/SBB transforms currently in combineX86SetCC() to combineAddOrSubToADCOrSBB() because we're creating ADC/SBB in lots of places where we shouldn't. This was intended to be an NFC change, but avx-512 has something strange going on. It doesn't seem like any of the affected tests should really be using SET+TEST or ADC; a simple ADD could replace several instructions. But that's another bug... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296978 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 5a71be4472e..d5a969f7d9f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -34103,51 +34103,56 @@ static SDValue combineADC(SDNode *N, SelectionDAG &DAG, /// then try to convert it to an ADC or SBB. This replaces TEST+SET+{ADD/SUB} /// with CMP+{ADC, SBB}. static SDValue combineAddOrSubToADCOrSBB(SDNode *N, SelectionDAG &DAG) { - // Look through ZExts. bool IsSub = N->getOpcode() == ISD::SUB; - SDValue Y = N->getOperand(0); - SDValue Ext = N->getOperand(1); + SDValue X = N->getOperand(0); + SDValue Y = N->getOperand(1); - // If this is an add, canonicalize a zext to the RHS. + // If this is an add, canonicalize a zext operand to the RHS. // TODO: Incomplete? What if both sides are zexts? - if (!IsSub && Ext.getOpcode() != ISD::ZERO_EXTEND && - Y.getOpcode() == ISD::ZERO_EXTEND) - std::swap(Ext, Y); + if (!IsSub && X.getOpcode() == ISD::ZERO_EXTEND && + Y.getOpcode() != ISD::ZERO_EXTEND) + std::swap(X, Y); - if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) - return SDValue(); + // Look through a one-use zext. + if (Y.getOpcode() == ISD::ZERO_EXTEND && Y.hasOneUse()) + Y = Y.getOperand(0); + + // If this is an add, canonicalize a setcc operand to the RHS. + // TODO: Incomplete? What if both sides are setcc? + if (!IsSub && X.getOpcode() == X86ISD::SETCC && + Y.getOpcode() != X86ISD::SETCC) + std::swap(X, Y); - SDValue SetCC = Ext.getOperand(0); - if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) + if (Y.getOpcode() != X86ISD::SETCC || !Y.hasOneUse()) return SDValue(); - X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); + X86::CondCode CC = (X86::CondCode)Y.getConstantOperandVal(0); if (CC != X86::COND_E && CC != X86::COND_NE) return SDValue(); - SDValue Cmp = SetCC.getOperand(1); + SDValue Cmp = Y.getOperand(1); if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || !X86::isZeroNode(Cmp.getOperand(1)) || !Cmp.getOperand(0).getValueType().isInteger()) return SDValue(); - // (cmp X, 1) sets the carry flag if X is 0. SDLoc DL(N); - SDValue X = Cmp.getOperand(0); - SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, X, - DAG.getConstant(1, DL, X.getValueType())); + EVT VT = N->getValueType(0); - EVT VT = Y.getValueType(); + // (cmp Z, 1) sets the carry flag if Z is 0. + SDValue Z = Cmp.getOperand(0); + SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, Z, + DAG.getConstant(1, DL, Z.getValueType())); - // Y - (X != 0) --> sub Y, (zext(setne X, 0)) --> adc Y, -1, (cmp X, 1) - // Y + (X != 0) --> add Y, (zext(setne X, 0)) --> sbb Y, -1, (cmp X, 1) + // X - (Z != 0) --> sub X, (zext(setne Z, 0)) --> adc X, -1, (cmp Z, 1) + // X + (Z != 0) --> add X, (zext(setne Z, 0)) --> sbb X, -1, (cmp Z, 1) if (CC == X86::COND_NE) - return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VT, Y, + return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VT, X, DAG.getConstant(-1ULL, DL, VT), NewCmp); - // Y - (X == 0) --> sub Y, (zext(sete X, 0)) --> sbb Y, 0, (cmp X, 1) - // Y + (X == 0) --> add Y, (zext(sete X, 0)) --> adc Y, 0, (cmp X, 1) - return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VT, Y, + // X - (Z == 0) --> sub X, (zext(sete Z, 0)) --> sbb X, 0, (cmp Z, 1) + // X + (Z == 0) --> add X, (zext(sete Z, 0)) --> adc X, 0, (cmp Z, 1) + return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VT, X, DAG.getConstant(0, DL, VT), NewCmp); } diff --git a/test/CodeGen/X86/avx512-insert-extract.ll b/test/CodeGen/X86/avx512-insert-extract.ll index aee4c6367e2..55b9bb9a9c7 100644 --- a/test/CodeGen/X86/avx512-insert-extract.ll +++ b/test/CodeGen/X86/avx512-insert-extract.ll @@ -1423,9 +1423,9 @@ define zeroext i8 @test_extractelement_v2i1(<2 x i64> %a, <2 x i64> %b) { ; SKX-NEXT: kshiftrw $15, %k0, %k0 ; SKX-NEXT: kmovw %k0, %eax ; SKX-NEXT: andl $1, %eax -; SKX-NEXT: testb %al, %al -; SKX-NEXT: sete %al -; SKX-NEXT: addb $3, %al +; SKX-NEXT: cmpb $1, %al +; SKX-NEXT: movb $3, %al +; SKX-NEXT: adcb $0, %al ; SKX-NEXT: movzbl %al, %eax ; SKX-NEXT: retq %t1 = icmp ugt <2 x i64> %a, %b @@ -1453,9 +1453,9 @@ define zeroext i8 @extractelement_v2i1_alt(<2 x i64> %a, <2 x i64> %b) { ; SKX-NEXT: kshiftrw $15, %k0, %k0 ; SKX-NEXT: kmovw %k0, %eax ; SKX-NEXT: andl $1, %eax -; SKX-NEXT: testb %al, %al -; SKX-NEXT: sete %al -; SKX-NEXT: addb $3, %al +; SKX-NEXT: cmpb $1, %al +; SKX-NEXT: movb $3, %al +; SKX-NEXT: adcb $0, %al ; SKX-NEXT: movzbl %al, %eax ; SKX-NEXT: retq %t1 = icmp ugt <2 x i64> %a, %b @@ -1535,9 +1535,9 @@ define zeroext i8 @test_extractelement_v64i1(<64 x i8> %a, <64 x i8> %b) { ; SKX-NEXT: kshiftrq $63, %k0, %k0 ; SKX-NEXT: kmovw %k0, %eax ; SKX-NEXT: andl $1, %eax -; SKX-NEXT: testb %al, %al -; SKX-NEXT: sete %al -; SKX-NEXT: addb $3, %al +; SKX-NEXT: cmpb $1, %al +; SKX-NEXT: movb $3, %al +; SKX-NEXT: adcb $0, %al ; SKX-NEXT: movzbl %al, %eax ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq @@ -1566,9 +1566,9 @@ define zeroext i8 @extractelement_v64i1_alt(<64 x i8> %a, <64 x i8> %b) { ; SKX-NEXT: kshiftrq $63, %k0, %k0 ; SKX-NEXT: kmovw %k0, %eax ; SKX-NEXT: andl $1, %eax -; SKX-NEXT: testb %al, %al -; SKX-NEXT: sete %al -; SKX-NEXT: addb $3, %al +; SKX-NEXT: cmpb $1, %al +; SKX-NEXT: movb $3, %al +; SKX-NEXT: adcb $0, %al ; SKX-NEXT: movzbl %al, %eax ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq