From: Amaury Sechet Date: Sat, 3 Jun 2017 11:35:40 +0000 (+0000) Subject: Regenerate expectations for trunc-to-bool.ll . NFC X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ec193781b1acc78a5448734ea17b83d227c160e6;p=llvm Regenerate expectations for trunc-to-bool.ll . NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304660 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/trunc-to-bool.ll b/test/CodeGen/X86/trunc-to-bool.ll index 3c99928824b..8e253f11e93 100644 --- a/test/CodeGen/X86/trunc-to-bool.ll +++ b/test/CodeGen/X86/trunc-to-bool.ll @@ -1,16 +1,32 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; An integer truncation to i1 should be done with an and instruction to make ; sure only the LSBit survives. Test that this is the case both for a returned ; value and as the operand of a branch. ; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s define zeroext i1 @test1(i32 %X) nounwind { +; CHECK-LABEL: test1: +; CHECK: # BB#0: +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al +; CHECK-NEXT: andb $1, %al +; CHECK-NEXT: retl %Y = trunc i32 %X to i1 ret i1 %Y } -; CHECK-LABEL: test1: -; CHECK: andb $1, %al define i1 @test2(i32 %val, i32 %mask) nounwind { +; CHECK-LABEL: test2: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx +; CHECK-NEXT: btl %ecx, %eax +; CHECK-NEXT: jae .LBB1_2 +; CHECK-NEXT: # BB#1: # %ret_true +; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB1_2: # %ret_false +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retl entry: %shifted = ashr i32 %val, %mask %anded = and i32 %shifted, 1 @@ -21,10 +37,19 @@ ret_true: ret_false: ret i1 false } -; CHECK-LABEL: test2: -; CHECK: btl define i32 @test3(i8* %ptr) nounwind { +; CHECK-LABEL: test3: +; CHECK: # BB#0: +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: testb $1, (%eax) +; CHECK-NEXT: je .LBB2_2 +; CHECK-NEXT: # BB#1: # %cond_true +; CHECK-NEXT: movl $21, %eax +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB2_2: # %cond_false +; CHECK-NEXT: movl $42, %eax +; CHECK-NEXT: retl %val = load i8, i8* %ptr %tmp = trunc i8 %val to i1 br i1 %tmp, label %cond_true, label %cond_false @@ -33,10 +58,18 @@ cond_true: cond_false: ret i32 42 } -; CHECK-LABEL: test3: -; CHECK: testb $1, (%eax) define i32 @test4(i8* %ptr) nounwind { +; CHECK-LABEL: test4: +; CHECK: # BB#0: +; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) +; CHECK-NEXT: je .LBB3_2 +; CHECK-NEXT: # BB#1: # %cond_true +; CHECK-NEXT: movl $21, %eax +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB3_2: # %cond_false +; CHECK-NEXT: movl $42, %eax +; CHECK-NEXT: retl %tmp = ptrtoint i8* %ptr to i1 br i1 %tmp, label %cond_true, label %cond_false cond_true: @@ -44,10 +77,29 @@ cond_true: cond_false: ret i32 42 } -; CHECK-LABEL: test4: -; CHECK: testb $1, 4(%esp) define i32 @test5(double %d) nounwind { +; CHECK-LABEL: test5: +; CHECK: # BB#0: +; CHECK-NEXT: pushl %eax +; CHECK-NEXT: fldl {{[0-9]+}}(%esp) +; CHECK-NEXT: fnstcw (%esp) +; CHECK-NEXT: movzwl (%esp), %eax +; CHECK-NEXT: movw $3199, (%esp) # imm = 0xC7F +; CHECK-NEXT: fldcw (%esp) +; CHECK-NEXT: movw %ax, (%esp) +; CHECK-NEXT: fistps {{[0-9]+}}(%esp) +; CHECK-NEXT: fldcw (%esp) +; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) +; CHECK-NEXT: je .LBB4_2 +; CHECK-NEXT: # BB#1: # %cond_true +; CHECK-NEXT: movl $21, %eax +; CHECK-NEXT: popl %ecx +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB4_2: # %cond_false +; CHECK-NEXT: movl $42, %eax +; CHECK-NEXT: popl %ecx +; CHECK-NEXT: retl %tmp = fptosi double %d to i1 br i1 %tmp, label %cond_true, label %cond_false cond_true: @@ -55,5 +107,3 @@ cond_true: cond_false: ret i32 42 } -; CHECK-LABEL: test5: -; CHECK: testb $1