From: Mikhail Maltsev <mikhail.maltsev@arm.com>
Date: Mon, 1 Jul 2019 16:07:58 +0000 (+0000)
Subject: [ARM] Fix MVE_VQxDMLxDH instruction class
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=ec01b2964e0b733881e2fdb359f6445d6072fe03;p=llvm

[ARM] Fix MVE_VQxDMLxDH instruction class

Summary:
According to the ARMARM, the VQDMLADH, VQRDMLADH, VQDMLSDH and
VQRDMLSDH instructions handle their results as follows: "The base
variant writes the results into the lower element of each pair of
elements in the destination register, whereas the exchange variant
writes to the upper element in each pair". I.e., the initial content
of the output register affects the result, as usual, we model this
with an additional input.

Also, for 32-bit variants Qd is not allowed to be the same register as
Qm and Qn, we use @earlyclobber to indicate this.

This patch also changes vpred_r to vpred_n because the instructions
don't have an explicit 'inactive' operand.

Reviewers: dmgreen, ostannard, simon_tatham

Reviewed By: simon_tatham

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64007

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364796 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMInstrMVE.td b/lib/Target/ARM/ARMInstrMVE.td
index a4221c5014e..5282e62e383 100644
--- a/lib/Target/ARM/ARMInstrMVE.td
+++ b/lib/Target/ARM/ARMInstrMVE.td
@@ -2747,10 +2747,13 @@ class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
 }
 
 class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
-                    string suffix, bits<2> size, list<dag> pattern=[]>
+                    string suffix, bits<2> size, bit earlyclobber,
+                    list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
-                   (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
-                   vpred_r, "", pattern> {
+                   (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
+                   vpred_n,
+                   !if(earlyclobber, "@earlyclobber $Qd,", "") # "$Qd = $Qd_src",
+                   pattern> {
   bits<4> Qn;
 
   let Inst{28} = subtract;
@@ -2765,9 +2768,9 @@ class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
 
 multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
                                bit round, bit subtract> {
-  def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00>;
-  def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
-  def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10>;
+  def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00, 0b0>;
+  def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01, 0b0>;
+  def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10, 0b1>;
 }
 
 defm MVE_VQDMLADH   : MVE_VQxDMLxDH_multi<"vqdmladh",   0b0, 0b0, 0b0>;