From: Francis Visoiu Mistrih <francisvm@yahoo.com>
Date: Thu, 7 Dec 2017 14:32:15 +0000 (+0000)
Subject: [CodeGen] Use more getMFIfAvailable
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=e8c40f01ad6c09825233fe50b04eee23d1462a7d;p=llvm

[CodeGen] Use more getMFIfAvailable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320046 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/MachineOperand.cpp b/lib/CodeGen/MachineOperand.cpp
index f5857db8ada..85b441c40ab 100644
--- a/lib/CodeGen/MachineOperand.cpp
+++ b/lib/CodeGen/MachineOperand.cpp
@@ -339,13 +339,9 @@ hash_code llvm::hash_value(const MachineOperand &MO) {
 static void tryToGetTargetInfo(const MachineOperand &MO,
                                const TargetRegisterInfo *&TRI,
                                const TargetIntrinsicInfo *&IntrinsicInfo) {
-  if (const MachineInstr *MI = MO.getParent()) {
-    if (const MachineBasicBlock *MBB = MI->getParent()) {
-      if (const MachineFunction *MF = MBB->getParent()) {
-        TRI = MF->getSubtarget().getRegisterInfo();
-        IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
-      }
-    }
+  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
+    TRI = MF->getSubtarget().getRegisterInfo();
+    IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
   }
 }
 
@@ -394,15 +390,11 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
     }
     // Print the register class / bank.
     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
-      if (const MachineInstr *MI = getParent()) {
-        if (const MachineBasicBlock *MBB = MI->getParent()) {
-          if (const MachineFunction *MF = MBB->getParent()) {
-            const MachineRegisterInfo &MRI = MF->getRegInfo();
-            if (!PrintDef || MRI.def_empty(Reg)) {
-              OS << ':';
-              OS << printRegClassOrBank(Reg, MRI, TRI);
-            }
-          }
+      if (const MachineFunction *MF = getMFIfAvailable(*this)) {
+        const MachineRegisterInfo &MRI = MF->getRegInfo();
+        if (!PrintDef || MRI.def_empty(Reg)) {
+          OS << ':';
+          OS << printRegClassOrBank(Reg, MRI, TRI);
         }
       }
     }