From: Craig Topper <craig.topper@intel.com>
Date: Mon, 18 Mar 2019 22:06:14 +0000 (+0000)
Subject: [X86] Disable CQTO and CLTQ instructions in the assembly parser outside 64-bit mode.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=e85ffd1263fef603e603bfc73ae9a8146ee09457;p=llvm

[X86] Disable CQTO and CLTQ instructions in the assembly parser outside 64-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356419 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td
index 0b06b3e58fd..06e605fe5db 100644
--- a/lib/Target/X86/X86InstrExtension.td
+++ b/lib/Target/X86/X86InstrExtension.td
@@ -28,11 +28,11 @@ let hasSideEffects = 0 in {
 
   let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
   def CDQE : RI<0x98, RawFrm, (outs), (ins),
-               "{cltq|cdqe}", []>, Sched<[WriteALU]>;
+               "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
 
   let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
   def CQO  : RI<0x99, RawFrm, (outs), (ins),
-                "{cqto|cqo}", []>, Sched<[WriteALU]>;
+                "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
 }
 
 // Sign/Zero extenders
diff --git a/test/MC/X86/x86_errors.s b/test/MC/X86/x86_errors.s
index d9995918389..273abd57fba 100644
--- a/test/MC/X86/x86_errors.s
+++ b/test/MC/X86/x86_errors.s
@@ -158,3 +158,9 @@ mov v_ecx(%eax), %ecx
 // 32: 7: error: invalid operand for instruction
 // 64: 7: error: invalid operand for instruction
 addb (%dx), %al
+
+// 32: error: instruction requires: 64-bit mode
+cqto
+
+// 32: error: instruction requires: 64-bit mode
+cltq