From: Ivan Grokhotkov <ivan@espressif.com>
Date: Tue, 21 Feb 2017 13:57:53 +0000 (+0800)
Subject: spi_flash: protect esp_intr_noniram_{disable,enable} in 1-core config
X-Git-Tag: v2.0-rc2~42^2~1
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=e76c187efb20facf8cad410aae5102a58d2e9145;p=esp-idf

spi_flash: protect esp_intr_noniram_{disable,enable} in 1-core config

MR !441 (7c155ab) has fixed issue with esp_intr_noniram_{disable,enable}
calls not being properly protected by spi_flash_op_{lock,unlock}.
Unit test was added, but the unit test environment tests only dual-core
config. Similar issue was present in the code path for the single-core
config, where esp_intr_noniram_{disable,enable} calls were unprotected.

This change fixes the protection issue and updates the unit test to
run properly in single core config as well.

The issue with running unit tests for single core config will be
addressed in a separate MR.
---

diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index df9d18c443..5e880ab493 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -205,16 +205,16 @@ void spi_flash_op_unlock()
 
 void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
 {
-    esp_intr_noniram_disable();
     spi_flash_op_lock();
+    esp_intr_noniram_disable();
     spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
 }
 
 void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
 {
     spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
-    spi_flash_op_unlock();
     esp_intr_noniram_enable();
+    spi_flash_op_unlock();
 }
 
 void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os()
diff --git a/components/spi_flash/test/test_spi_flash.c b/components/spi_flash/test/test_spi_flash.c
index 90d0cc1fdc..597568ec6a 100644
--- a/components/spi_flash/test/test_spi_flash.c
+++ b/components/spi_flash/test/test_spi_flash.c
@@ -65,19 +65,24 @@ static void flash_test_task(void *arg)
 TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_flash][ignore]")
 {
     SemaphoreHandle_t done = xSemaphoreCreateCounting(4, 0);
-    struct flash_test_ctx ctx[4] = {
+    struct flash_test_ctx ctx[] = {
             { .offset = 0x100 + 6, .done = done },
             { .offset = 0x100 + 7, .done = done },
             { .offset = 0x100 + 8, .done = done },
+#ifndef CONFIG_FREERTOS_UNICORE
             { .offset = 0x100 + 9, .done = done }
+#endif
     };
 
-    xTaskCreatePinnedToCore(flash_test_task, "1", 2048, &ctx[0], 3, NULL, 0);
-    xTaskCreatePinnedToCore(flash_test_task, "2", 2048, &ctx[1], 3, NULL, 1);
-    xTaskCreatePinnedToCore(flash_test_task, "3", 2048, &ctx[2], 3, NULL, tskNO_AFFINITY);
-    xTaskCreatePinnedToCore(flash_test_task, "4", 2048, &ctx[3], 3, NULL, tskNO_AFFINITY);
+    xTaskCreatePinnedToCore(flash_test_task, "t0", 2048, &ctx[0], 3, NULL, 0);
+    xTaskCreatePinnedToCore(flash_test_task, "t1", 2048, &ctx[1], 3, NULL, tskNO_AFFINITY);
+    xTaskCreatePinnedToCore(flash_test_task, "t2", 2048, &ctx[2], 3, NULL, tskNO_AFFINITY);
+#ifndef CONFIG_FREERTOS_UNICORE
+    xTaskCreatePinnedToCore(flash_test_task, "t3", 2048, &ctx[3], 3, NULL, 1);
+#endif
 
-    for (int i = 0; i < 4; ++i) {
+    const size_t task_count = sizeof(ctx)/sizeof(ctx[0]);
+    for (int i = 0; i < task_count; ++i) {
         xSemaphoreTake(done, portMAX_DELAY);
         TEST_ASSERT_FALSE(ctx[i].fail);
     }